SLLSF47C
February 2018 – October 2018
TUSB1044
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Simplified Schematic
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Timing Requirements
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
USB 3.1
7.3.2
DisplayPort
7.3.3
4-level Inputs
7.3.4
Receiver Linear Equalization
7.4
Device Functional Modes
7.4.1
Device Configuration in GPIO mode
7.4.2
Device Configuration in I2C Mode
7.4.3
DisplayPort Mode
7.4.4
Custom Alternate Mode
7.4.5
Linear EQ Configuration
7.4.6
Adjustable VOD Linear Range and DC Gain
7.4.7
USB3.1 Modes
7.5
Programming
7.5.1
Use The Following Procedure to Write to TUSB1044 I2C Registers:
7.5.2
Use The Following Procedure to Read the TUSB1044 I2C Registers:
7.5.3
Use The Following Procedure for Setting a Starting Sub-Address for I2C Reads:
7.6
Register Maps
7.6.1
TUSB1044 Registers
7.6.1.1
General_1 Register (Offset = Ah) [reset = 1h]
Table 12.
General_1 Register Field Descriptions
7.6.1.2
General_2 Register (Offset = Bh) [reset = 0h]
Table 13.
General_2 Register Field Descriptions
7.6.1.3
General_3 Register (Offset = Ch) [reset = 0h]
Table 14.
General_3 Register Field Descriptions
7.6.1.4
UFP2_EQ Register (Offset = 10h) [reset = 0h]
Table 15.
UFP2_EQ Register Field Descriptions
7.6.1.5
UFP1_EQ Register (Offset = 11h) [reset = 0h]
Table 16.
UFP1_EQ Register Field Descriptions
7.6.1.6
DisplayPort_1 Register (Offset = 12h) [reset = 0h]
Table 17.
DisplayPort_1 Register Field Descriptions
7.6.1.7
DisplayPort_2 Register (Offset = 13h) [reset = 0h]
Table 18.
DisplayPort_2 Register Field Descriptions
7.6.1.8
SOFT_RESET Register (Offset = 1Bh) [reset = 0h]
Table 19.
SOFT_RESET Register Field Descriptions
7.6.1.9
DFP2_EQ Register (Offset = 20h) [reset = 0h]
Table 20.
DFP2_EQ Register Field Descriptions
7.6.1.10
DFP1_EQ Register (Offset = 21h) [reset = 0h]
Table 21.
DFP1_EQ Register Field Descriptions
7.6.1.11
USB3_MISC Register (Offset = 22h) [reset = 4h]
Table 22.
USB3_MISC Register Field Descriptions
7.6.1.12
USB3_LOS Register (Offset = 23h) [reset = 23h]
Table 23.
USB3_LOS Register Field Descriptions
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
8.3
System Examples
8.3.1
USB 3.1 only (USB/DP Alternate Mode)
8.3.2
USB3.1 and 2 lanes of DisplayPort
8.3.3
DisplayPort Only
8.3.4
USB 3.1 only (USB/Custom Alternate Mode)
8.3.5
USB3.1 and 1 Lane of Custom Alt Mode
8.3.6
USB3.1 and 2 Lane of Custom Alt Mode
8.3.7
USB3.1 and 4 Lane of Custom Alt Mode
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
Community Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RNQ|40
MPQF457A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sllsf47c_oa
sllsf47c_pm
8.3.3
DisplayPort Only
Figure 42.
Four Lane DP – No Flip
Figure 43.
Four Lane DP – With Flip