SLLSFZ7 February   2025 TUSB1146-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Supply Characteristics
    6. 5.6  Control I/O DC Electrical Characteristics
    7. 5.7  USB and DP Electrical Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 USB 3.2
      2. 6.3.2 DisplayPort
      3. 6.3.3 4-Level Inputs
      4. 6.3.4 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO Mode
      2. 6.4.2 Device Configuration In I2C Mode
      3. 6.4.3 DisplayPort Mode
      4. 6.4.4 Linear EQ Configuration
      5. 6.4.5 Linearity VOD
      6. 6.4.6 VOD Modes
        1. 6.4.6.1 Linearity VOD
        2. 6.4.6.2 Limited VOD
      7. 6.4.7 Transmit Equalization
      8. 6.4.8 USB3.2 Modes
      9. 6.4.9 Downstream Facing Port Adaptive Equalization
        1. 6.4.9.1 Fast Adaptive Equalization in I2C Mode
        2. 6.4.9.2 Full Adaptive Equalization
        3. 6.4.9.3 Full Adaptive Equalization in GPIO Mode (I2C_EN = "F")
    5. 6.5 Programming
      1. 6.5.1 Transition Between Modes
      2. 6.5.2 Pseudocode Examples
        1. 6.5.2.1 Fast AEQ With Linear Redriver Mode
        2. 6.5.2.2 Fast AEQ With Limited Redriver Mode
        3. 6.5.2.3 Full AEQ With Linear Redriver Mode
        4. 6.5.2.4 Full AEQ With Limited Redriver Mode
      3. 6.5.3 TUSB1146-Q1 I2C Address Options
      4. 6.5.4 TUSB1146-Q1 I2C Target Behavior
  9. 7 Register Maps
    1. 7.1 TUSB1146-Q1 Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 USB and DP Upstream Facing Port (USB Host / DP GPU to USB-C Receptacle) Configuration
        2. 8.2.2.2 USB Downstream Facing Port (USB-C Receptacle to USB Host) Configuration
          1. 8.2.2.2.1 Fixed Equalization
          2. 8.2.2.2.2 Fast Adaptive Equalization
          3. 8.2.2.2.3 Full Adaptive Equalization
        3. 8.2.2.3 ESD Protection
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2-Lane DisplayPort Mode
      3. 8.3.3 DisplayPort Only
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5.4 TUSB1146-Q1 I2C Target Behavior

TUSB1146-Q1 I2C Write With DataFigure 6-2 I2C Write With Data

Use the following procedure to write data to TUSB1146-Q1 I2C registers (refer to Figure 6-2):

  1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB1146-Q1 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TUSB1146-Q1 acknowledges the address cycle.
  3. The controller presents the register offset within TUSB1146-Q1 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB1146-Q1 acknowledges the sub-address cycle.
  5. The controller presents the first byte of data to be written to the I2C register.
  6. The TUSB1146-Q1 acknowledges the byte transfer
  7. The controller can continue to present additional bytes of data to be written, where each byte transfer is complete after an acknowledge from the TUSB1146-Q1.
  8. The controller terminates the write operation by generating a stop condition (P).

TUSB1146-Q1 I2C Read Without Repeated StartFigure 6-3 I2C Read Without Repeated Start

Use the following procedure to read the TUSB1146-Q1 I2C registers without a repeated Start (refer Figure 6-3).

  1. The controller initiates a read operation by generating a start condition (S), followed by the TUSB1146-Q1 7-bit address and a zero-value “W/R” bit to indicate a read cycle.
  2. The TUSB1146-Q1 acknowledges the 7-bit address cycle.
  3. Following the acknowledge the controller continues sending clock.
  4. The TUSB1146-Q1 transmit the contents of the memory registers MSB-first starting at register 00h or last read register offset+1. If a write to the I2C register occurred prior to the read, then the TUSB1146-Q1 shall start at the register offset specified in the write.
  5. The TUSB1146-Q1 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.
  6. If an ACK is received, the TUSB1146-Q1 transmits the next byte of data as long as the controller provides the clock. If a NAK is received, the TUSB1146-Q1 stops providing data and waits for a stop condition (P).
  7. The controller terminates the write operation by generating a stop condition (P).

TUSB1146-Q1 I2C Read With Repeated StartFigure 6-4 I2C Read With Repeated Start

Use the following procedure to read the TUSB1146-Q1 I2C registers with a repeated Start (refer Figure 6-4).

  1. The controller initiates a read operation by generating a start condition (S), followed by the TUSB1146-Q1 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TUSB1146-Q1 acknowledges the 7-bit address cycle.
  3. The controller presents the register offset within TUSB1146-Q1 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB1146-Q1 acknowledges the register offset cycle.
  5. The controller presents a repeated start condition (Sr).
  6. The controller initiates a read operation by generating a start condition (S), followed by the TUSB1146-Q1 7-bit address and a one-value “W/R” bit to indicate a read cycle.
  7. The TUSB1146-Q1 acknowledges the 7-bit address cycle.
  8. The TUSB1146-Q1 transmit the contents of the memory registers MSB-first starting at the register offset.
  9. The TUSB1146-Q1 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.
  10. If an ACK is received, the TUSB1146-Q1 transmits the next byte of data as long as the controller provides the clock. If a NAK is received, the TUSB1146-Q1 stops providing data and waits for a stop condition (P).
  11. The controller terminates the read operation by generating a stop condition (P).

TUSB1146-Q1 I2C Write Without DataFigure 6-5 I2C Write Without Data

Use the following procedure to set a starting sub-address for I2C reads (refer to Figure 6-5).

  1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB1146-Q1 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TUSB1146-Q1 acknowledges the address cycle.
  3. The controller presents the register offset within TUSB1146-Q1 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB1146-Q1 acknowledges the register offset cycle.
  5. The controller terminates the write operation by generating a stop condition (P).

Note:

After initial power-up, if no register offset is included for the read procedure (refer to Figure 6-3), then reads start at register offset 00h and continue byte by byte through the registers until the I2C controller terminates the read operation. During a read operation, the TUSB1146-Q1 auto-increments the I2C internal register address of the last byte transferred independent of whether or not an ACK was received from the I2C controller.