SLLSEL4A
September 2014 – October 2014
TUSB1210-Q1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
Handling Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Analog I/O Electrical Characteristics
6.6
Digital I/O Electrical Characteristics
6.7
Digital IO Pins (Non-ULPI)
6.8
PHY Electrical Characteristics
6.9
Pullup/Pulldown Resistors
6.10
OTG Electrical Characteristics
6.11
Power Characteristics
6.12
Switching Characteristics
6.13
Timing Requirements
6.13.1
Timing Parameter Definitions
6.13.2
Interface Target Frequencies
6.14
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Processor Subsystem
7.3.1.1
Clock Specifications
7.3.1.1.1
USB PLL Reference Clock
7.3.1.1.2
ULPI Input Clock Configuration
7.3.1.1.3
ULPI Output Clock Configuration
7.3.1.1.4
Clock 32 kHz
7.3.1.1.5
Reset
7.3.1.2
USB Transceiver
7.3.1.2.1
PHY Electrical Characteristics
7.3.1.2.1.1
LS/FS Single-Ended Receivers
7.3.1.2.1.2
LS/FS Differential Receiver
7.3.1.2.1.3
LS/FS Transmitter
7.3.1.2.1.4
HS Differential Receiver
7.3.1.2.1.5
HS Differential Transmitter
7.3.1.2.1.6
UART Transceiver
7.3.1.2.2
OTG Characteristics
7.4
Device Functional Modes
7.4.1
TUSB1210-Q1 Modes vs ULPI Pin Status
7.5
Register Map
7.5.1
VENDOR_ID_LO
7.5.2
VENDOR_ID_HI
7.5.3
PRODUCT_ID_LO
7.5.4
PRODUCT_ID_HI
7.5.5
FUNC_CTRL
7.5.6
FUNC_CTRL_SET
7.5.7
FUNC_CTRL_CLR
7.5.8
IFC_CTRL
7.5.9
IFC_CTRL_SET
7.5.10
IFC_CTRL_CLR
7.5.11
OTG_CTRL
7.5.12
OTG_CTRL_SET
7.5.13
OTG_CTRL_CLR
7.5.14
USB_INT_EN_RISE
7.5.15
USB_INT_EN_RISE_SET
7.5.16
USB_INT_EN_RISE_CLR
7.5.17
USB_INT_EN_FALL
7.5.18
USB_INT_EN_FALL_SET
7.5.19
USB_INT_EN_FALL_CLR
7.5.20
USB_INT_STS
7.5.21
USB_INT_LATCH
7.5.22
DEBUG
7.5.23
SCRATCH_REG
7.5.24
SCRATCH_REG_SET
7.5.25
SCRATCH_REG_CLR
7.5.26
VENDOR_SPECIFIC1
7.5.27
VENDOR_SPECIFIC1_SET
7.5.28
VENDOR_SPECIFIC1_CLR
7.5.29
VENDOR_SPECIFIC2
7.5.30
VENDOR_SPECIFIC2_SET
7.5.31
VENDOR_SPECIFIC2_CLR
7.5.32
VENDOR_SPECIFIC1_STS
7.5.33
VENDOR_SPECIFIC1_LATCH
7.5.34
VENDOR_SPECIFIC3
7.5.35
VENDOR_SPECIFIC3_SET
7.5.36
VENDOR_SPECIFIC3_CLR
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Host or OTG, ULPI Input Clock Mode Application
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
Unused Pins Connection
8.2.1.3
Application Curve
8.2.2
Device, ULPI Output Clock Mode Application
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.2.1
Unused Pins Connection
8.2.2.3
Application Curve
8.3
External Components
9
Power Supply Recommendations
9.1
TUSB1210 Power Supply
9.2
Ground
9.3
Power Providers
9.4
Power Modules
9.4.1
VDD33 Regulator
9.4.2
VDD18 Supply
9.4.3
VDD15 Regulator
9.5
Power Consumption
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.2
Community Resources
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
11.5.1
Glossary
12
Mechanical, Packaging, and Orderable Information
12.1
Via Channel
12.2
Packaging Information
Package Options
Mechanical Data (Package|Pins)
RHB|32
MPQF130D
Thermal pad, mechanical data (Package|Pins)
RHB|32
QFND029X
Orderable Information
sllsel4a_oa
sllsel4a_pm