SLLSE80B March   2011  – June 2015 TUSB1211

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Diagram
      1. 3.1.1 Pin Attributes
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Power Consumption Summary
    5. 4.5  Electrical Characteristics - Analog Output Pins
    6. 4.6  Electrical Characteristics - Analog Input Pins
    7. 4.7  Digital I/O Electrical Characteristics - Non-ULPI Pins
    8. 4.8  Digital I/O Electrical Characteristics - Non-ULPI Pins
    9. 4.9  Electrical Characteristics - REFCLK
    10. 4.10 Electrical Characteristics - CLOCK Input
    11. 4.11 Electrical Characteristics - REFCLK
    12. 4.12 Electrical Characteristics - CK32K Clock Generator
    13. 4.13 Thermal Characteristics
    14. 4.14 REG3V3 Internal LDO Regulator Characteristics
    15. 4.15 REG1V8 Internal LDO Regulator Characteristics
    16. 4.16 REG1V5 Internal LDO Regulator Characteristics
    17. 4.17 Timers and Debounce
    18. 4.18 OTG VBUS Electrical
    19. 4.19 LS/FS Single-Ended Receivers
    20. 4.20 LS/FS Differential Receiver
    21. 4.21 LS Transmitter
    22. 4.22 FS Transmitter
    23. 4.23 HS Transmitter
    24. 4.24 Pullup and Pulldown Resistors
    25. 4.25 Autoresume Watchdog Timer
    26. 4.26 UART Transceiver
    27. 4.27 OTG ID Electrical
    28. 4.28 Electrical Specs - Charger Detection Currents
    29. 4.29 Electrical Specs - Resistance
    30. 4.30 Electrical Specs - Capacitance
    31. 4.31 Charger Detection Debounce and Wait Timing
    32. 4.32 ULPI Interface
      1. 4.32.1 ULPI Interface Timing
    33. 4.33 Power-On Timing Diagrams
      1. 4.33.1 Standard Power-up Timing
      2. 4.33.2 Hardware Charger Detection Power-Up Timing
    34. 4.34 Clock System
      1. 4.34.1 USB PLL Reference Clock
        1. 4.34.1.1 ULPI Input Clock Configuration
        2. 4.34.1.2 ULPI Output Clock Configuration
    35. 4.35 Clock System
      1. 4.35.1 Internal Clock Generator (32 kHz)
    36. 4.36 Power Management
      1. 4.36.1 Power Provider
    37. 4.37 Power Provider
      1. 4.37.1 REG3V3 Regulator
      2. 4.37.2 REG1V8 Regulator
      3. 4.37.3 REG1V5 Regulator
    38. 4.38 Power Control
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1  USB On-The-Go (OTG) Feature
      2. 5.3.2  VBUS Detection Status Bits vs VBUS Comparators
      3. 5.3.3  USB Transceiver (PHY)
        1. 5.3.3.1 PHY Overview
      4. 5.3.4  LS/FS Single-Ended Receivers
      5. 5.3.5  LS/FS Differential Receiver
      6. 5.3.6  LS/FS Transmitter
      7. 5.3.7  HS Differential Receiver
      8. 5.3.8  HS Differential Transmitter
      9. 5.3.9  Autoresume
      10. 5.3.10 UART Transceiver
      11. 5.3.11 USB On-The-Go (OTG)
        1. 5.3.11.1 ID Detection Status Bits vs ID Comparators
      12. 5.3.12 USB Battery Charger Detection and ACA
      13. 5.3.13 USB Battery Charger Detection Modes
      14. 5.3.14 Accessory Charger Adapter (ACA) Detection
    4. 5.4 Register Maps
      1. 5.4.1  VENDOR_ID_LO
      2. 5.4.2  VENDOR_ID_HI
      3. 5.4.3  PRODUCT_ID_LO
      4. 5.4.4  PRODUCT_ID_HI
      5. 5.4.5  FUNC_CTRL
      6. 5.4.6  FUNC_CTRL_SET
      7. 5.4.7  FUNC_CTRL_CLR
      8. 5.4.8  IFC_CTRL
      9. 5.4.9  IFC_CTRL_SET
      10. 5.4.10 IFC_CTRL_CLR
      11. 5.4.11 OTG_CTRL
      12. 5.4.12 OTG_CTRL_SET
      13. 5.4.13 OTG_CTRL_CLR
      14. 5.4.14 USB_INT_EN_RISE
      15. 5.4.15 USB_INT_EN_RISE_SET
      16. 5.4.16 USB_INT_EN_RISE_CLR
      17. 5.4.17 USB_INT_EN_FALL
      18. 5.4.18 USB_INT_EN_FALL_SET
      19. 5.4.19 USB_INT_EN_FALL_CLR
      20. 5.4.20 USB_INT_STS
      21. 5.4.21 USB_INT_LATCH
      22. 5.4.22 DEBUG
      23. 5.4.23 SCRATCH_REG
      24. 5.4.24 SCRATCH_REG_SET
      25. 5.4.25 SCRATCH_REG_CLR
      26. 5.4.26 POWER_CONTROL
      27. 5.4.27 POWER_CONTROL_SET
      28. 5.4.28 POWER_CONTROL_CLR
      29. 5.4.29 VENDOR_SPECIFIC1
      30. 5.4.30 VENDOR_SPECIFIC1_SET
      31. 5.4.31 VENDOR_SPECIFIC1_CLR
      32. 5.4.32 VENDOR_SPECIFIC2_STS
      33. 5.4.33 VENDOR_SPECIFIC2_LATCH
      34. 5.4.34 VENDOR_SPECIFIC3
      35. 5.4.35 VENDOR_SPECIFIC3_SET
      36. 5.4.36 VENDOR_SPECIFIC3_CLR
      37. 5.4.37 VENDOR_SPECIFIC4
      38. 5.4.38 VENDOR_SPECIFIC4_SET
      39. 5.4.39 VENDOR_SPECIFIC4_CLR
      40. 5.4.40 VENDOR_SPECIFIC5
      41. 5.4.41 VENDOR_SPECIFIC5_SET
      42. 5.4.42 VENDOR_SPECIFIC5_CLR
      43. 5.4.43 VENDOR_SPECIFIC6
      44. 5.4.44 VENDOR_SPECIFIC6_SET
      45. 5.4.45 VENDOR_SPECIFIC6_CLR
  6. 6Application, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Unused Pins Connection
      3. 6.2.3 Application Curves
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
        1. 6.3.1.1 Ground
      2. 6.3.2 Layout Example
    4. 6.4 Power Supply Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
      2. 7.1.2 Community Resources
    2. 7.2 Trademarks
    3. 7.3 Electrostatic Discharge Caution
    4. 7.4 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Device Overview

1.1 Features

  • USB2.0 PHY Transceiver Chip, Designed to Interface With a USB Controller Through a ULPI Interface, Fully Compliant With:
    • Universal Serial Bus Specification Rev. 2.0
    • On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3
    • UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1
  • DP/DM Line External Component Compensation (Patent #US7965100 B1)
  • Interfaces to Host, Peripheral, and OTG Device Cores; Optimized for Portable Devices or System ASICs With Built-in USB OTG Device Core
  • Complete USB OTG Physical Front-End
  • USB Battery Charger Detection Feature
  • USB HS Start-of-Frame Clock Output Feature Available on SOF Pin Can be Used to Synchronize Another Application, for Example Audio, With the USB Packet Stream
  • ULPI Interface:
    • I/O Interface (1.8 V) Optimized for Non-Terminated 50-Ω Line Impedance
    • ULPI CLOCK Pin (60 MHz) Supports Both Input and Output Clock Configurations
    • Fully Programmable ULPI-Compliant Register Set
  • Full Industrial-Grade Operating Temperature Range from –40°C to 85°C
  • Available in a TFBGA36 Ball Package

1.2 Applications

  • Mobile Phones
  • Portable Computers
  • Tablet Devices
  • Video Game Consoles
  • Desktop Computers
  • Portable Music Payers

1.3 Description

The TUSB1211 device is a USB2.0 transceiver chip, designed to interface with a USB controller through a ULPI interface. The device supports all USB2.0 data rates (high-speed 480 Mbps, full-speed 12 Mbps and low-speed 1.5 Mbps), and is compliant to both Host and Peripheral modes. The TUSB1211 also supports a UART mode and legacy ULPI serial modes.

The TUSB1211 device supports the OTG (Ver1.3) optional addendum to the USB 2.0 Specification, including Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). TUSB1211 also supports USB Battery Charging Specification Ver1.1 integrating a charger detection module for sensing and control on DP/DM lines, and ACA (Accessory Charger Adapter) detection and control on ID line.

The DP/DM external component compensation in the transmitter compensates for variations in the series impendence to match with the data line impedance and the receiver input impedance, to limit data reflections and, thereby, improve eye diagrams.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TUSB1211 BGA MICROSTAR JUNIOR (36) 3.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.

1.4 Functional Block Diagram

TUSB1211 bd_llse44.gif