SLLSEZ6C February   2019  – October 2020 TUSB216

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High-speed Boost
      2. 7.3.2 RX Sensitivity
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low-speed (LS) Mode
      2. 7.4.2 Full-speed (FS) Mode
      3. 7.4.3 High-speed (HS) Mode
      4. 7.4.4 High-speed Downstream Port Electrical Compliance Test Mode
      5. 7.4.5 Shutdown Mode
      6. 7.4.6 I2C Mode
      7. 7.4.7 BC 1.2 Battery Charging Controller
    5. 7.5 TUSB216 Registers
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Test Procedure to Construct USB High-speed Eye Diagram
          1. 8.2.2.1.1 For a Host Side Application
          2. 8.2.2.1.2 For a Device Side Application
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Timing Requirements

MINNOMMAXUNIT
POWER UP TIMING
TRSTN_PWMinimum width to detect a valid RSTN signal assert when the pin is actively driven low100µs
TSTABLEVCC must be stable before RSTN de-assertion300µs
TREADYMaximum time needed for the device to be ready after RSTN is de-asserted.500µs
TRAMPVCC ramp time100ms
TRAMPVCC ramp time0.2ms
I2C (STD)
tSUSTOStop setup time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz STD 4  µs
tHDSTAStart hold time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz STD4  µs
tSUSTAStart setup time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz STD4.7µs
tSUDATData input or False start/stop, setup time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz STD250ns
tHDDATData input or False start/stop, hold time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz STD5µs
tBUFBus free time between START and STOP conditions4.7µs
tLOWLow period of the I2C clock4.7µs
tHIGHHigh period of the I2C clock4µs
tFFall time of both SDA and SCL signals300ns
tRRise time of both SDA and SCL signals1000ns
GUID-978BA886-139B-47AC-98DB-B67B12946FE3-low.gifFigure 6-1 Power On and Reset Timing
GUID-409CA334-F138-4BA6-92F5-4AAF1D964D98-low.gifFigure 6-2 I2C Timing