SLLSEW6C November 2016 – June 2018 TUSB422
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
This register controls whether or not a status change event in Alert register will cause the INT_N to be asserted low. When a specific event is masked, its corresponding status change event will not cause INT_N to be asserted low.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBUS_ALARM_HI_MASK | TX_SOP_SUCCESS_MASK | TX_SOP_DISCARD_MASK | TX_SOP_FAIL_MASK | RX_HARD_RESET_MASK | RX_SOP_STATUS_MASK | PWR_STATUS_MASK | CC_STATUS_MASK |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | VBUS_ALARM_HI_MASK | R/W | 1 | VBUS Voltage Alarm Hi
0b: Interrupt masked 1b: Interrupt unmasked |
6 | TX_SOP_SUCCESS_MASK | R/W | 1 | Transmit SOP* Message successful Interrupt Mask
0b: Interrupt masked 1b: Interrupt unmasked |
5 | TX_SOP_DISCARD_MASK | R/W | 1 | Transmit SOP* Message discarded Interrupt Mask
0b: Interrupt masked 1b: Interrupt unmasked |
4 | TX_SOP_FAIL_MASK | R/W | 1 | Transmit SOP* Message failed Interrupt Mask
0b: Interrupt masked 1b: Interrupt unmasked |
3 | RX_HARD_RESET_MASK | R/W | 1 | Received Hard Reset Message Status Interrupt Mask
0b: Interrupt masked 1b: Interrupt unmasked |
2 | RX_SOP_STATUS_MASK | R/W | 1 | Receive SOP* Message Status Interrupt Mask
0b: Interrupt masked 1b: Interrupt unmasked |
1 | PWR_STATUS_MASK | R/W | 1 | Power Status Interrupt Mask
0b: Interrupt masked 1b: Interrupt unmasked |
0 | CC_STATUS_MASK | R/W | 1 | CC Status Interrupt Mask
0b: Interrupt masked 1b: Interrupt unmasked |