SLLSEW6C November 2016 – June 2018 TUSB422
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
This register controls whether or not a status change event in Alert register will cause the INT_N to be asserted low. When a specific event is masked, its corresponding status change event will not cause INT_N to be asserted low.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBUS_AIRQ_MASK | Reserved | VBUS_SINK_DIS_MASK | RX_BUF_OVR_MASK | FAULT_MASK | VBUS_ALARM_LO_MASK | ||
R/W | R | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | VBUS_IRO_MASK | R/W | 1 | Vendor Defined interrupt mask. . When this field is set to a 1’b1, the unmasked vendor interrupts can cause INT_N to be asserted.
0b: Interrupt masked 1b: Interrupt unmasked |
6:4 | Reserved | R | 0x0 | Reserved |
3 | VBUS_SINK_DIS_MASK | R/W | 1 | VBUS Sink Disconnect Detected Mask
0b: Interrupt masked 1b: Interrupt unmasked |
2 | RX_BUF_OVR_MASK | R/W | 1 | Rx Buffer Overflow Mask
0b: Interrupt masked 1b: Interrupt unmasked |
1 | FAULT_MASK | R/W | 1 | Fault Mask
0b: Interrupt masked 1b: Interrupt unmasked |
0 | VBUS_ALARM_LO_MASK | R/W | 1 | VBUS Voltage Alarm Lo Mask
0b: Interrupt masked 1b: Interrupt unmasked |