SLLSF93 June   2019 TUSB8042A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 One Time Programmable (OTP) Configuration
      4. 8.3.4 Clock Generation
      5. 8.3.5 Crystal Requirements
      6. 8.3.6 Input Clock Requirements
      7. 8.3.7 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 Port Configuration
      4. 8.4.4 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1  Configuration Registers
      2. 8.5.2  ROM Signature Register
        1. Table 6. Bit Descriptions – ROM Signature Register
      3. 8.5.3  Vendor ID LSB Register
        1. Table 7. Bit Descriptions – Vendor ID LSB Register
      4. 8.5.4  Vendor ID MSB Register
        1. Table 8. Bit Descriptions – Vendor ID MSB Register
      5. 8.5.5  Product ID LSB Register
        1. Table 9. Bit Descriptions – Product ID LSB Register
      6. 8.5.6  Product ID MSB Register
        1. Table 10. Bit Descriptions – Product ID MSB Register
      7. 8.5.7  Device Configuration Register
        1. Table 11. Bit Descriptions – Device Configuration Register
      8. 8.5.8  Battery Charging Support Register
        1. Table 12. Bit Descriptions – Battery Charging Support Register
      9. 8.5.9  Device Removable Configuration Register
        1. Table 13. Bit Descriptions – Device Removable Configuration Register
      10. 8.5.10 Port Used Configuration Register
        1. Table 14. Bit Descriptions – Port Used Configuration Register
      11. 8.5.11 Device Configuration Register 2
        1. Table 15. Bit Descriptions – Device Configuration Register 2
      12. 8.5.12 USB 2.0 Port Polarity Control Register
        1. Table 16. Bit Descriptions – USB 2.0 Port Polarity Control Register
      13. 8.5.13 UUID Registers
        1. Table 17. Bit Descriptions – UUID Byte N Register
      14. 8.5.14 Language ID LSB Register
        1. Table 18. Bit Descriptions – Language ID LSB Register
      15. 8.5.15 Language ID MSB Register
        1. Table 19. Bit Descriptions – Language ID MSB Register
      16. 8.5.16 Serial Number String Length Register
        1. Table 20. Bit Descriptions – Serial Number String Length Register
      17. 8.5.17 Manufacturer String Length Register
        1. Table 21. Bit Descriptions – Manufacturer String Length Register
      18. 8.5.18 Product String Length Register
        1. Table 22. Bit Descriptions – Product String Length Register
      19. 8.5.19 Device Configuration Register 3
        1. Table 23. Bit Descriptions – Device Configuration Register 3
      20. 8.5.20 USB 2.0 Only Port Register
        1. Table 24. Bit Descriptions – USB 2.0 Only Port Register
      21. 8.5.21 Serial Number String Registers
        1. Table 25. Bit Descriptions – Serial Number Registers
      22. 8.5.22 Manufacturer String Registers
        1. Table 26. Bit Descriptions – Manufacturer String Registers
      23. 8.5.23 Product String Registers
        1. Table 27. Bit Descriptions – Product String Byte N Register
      24. 8.5.24 Additional Feature Configuration Register
        1. Table 28. Bit Descriptions – Additional Feature Configuration Register
      25. 8.5.25 SMBus Device Status and Command Register
        1. Table 29. Bit Descriptions – SMBus Device Status and Command Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Discrete USB Hub Product
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Upstream Port Implementation
          2. 9.2.1.2.2 Downstream Port 1 Implementation
          3. 9.2.1.2.3 Downstream Port 2 Implementation
          4. 9.2.1.2.4 Downstream Port 3 Implementation
          5. 9.2.1.2.5 Downstream Port 4 Implementation
          6. 9.2.1.2.6 VBUS Power Switch Implementation
          7. 9.2.1.2.7 Clock, Reset, and Misc
          8. 9.2.1.2.8 TUSB8042A Power Implementation
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 TUSB8042A Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Examples
      1. 11.2.1 Upstream Port
      2. 11.2.2 Downstream Port
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.11 Device Configuration Register 2

Figure 12. Register Offset Ah
Bit No. 7 6 5 4 3 2 1 0
Reset State 0 0 X 0 0 0 0 0

Table 15. Bit Descriptions – Device Configuration Register 2

Bit Field Type Description
7 Reserved RO Reserved. Read-only, returns 0 when read.
6 customBCfeatures RW Custom Battery Charging Feature Enable. This bit controls the ability to write to the battery charging feature configuration controls.
0 = The HiCurAcpModeEn is read only and the values are loaded from the OTP ROM.
1 = The HiCurAcpModeEn bit is read/write and can be loaded by EEPROM or written by SMBus.
This bit may be written simultaneously with HiCurAcpModeEn.
5 pwrctlPol RW Power enable polarity. This bit is loaded at the de-assertion of reset with the value of the PWRCTL_POL pin.
0 = PWRCTL polarity is active low
1 = PWRCTL polarity is active high
When the TUSB8042A is in I2C mode, the TUSB8042A loads this bit from the contents of the EEPROM.
When the TUSB8042A is in SMBUS mode, the value may be over-written by an SMBus host.
4 HiCurAcpModeEn RO/RW High-current ACP mode enable. This bit enables the high-current tablet charging mode when the automatic battery charging mode is enabled for downstream ports.
0 = High current divider mode disabled . High current is ACP2(default)
1 = High current divider mode enabled. High current mode is ACP3
This bit is read only unless the customBCfeatures bit is set to 1. If customBCfeatures is 0, the value of this bit reflects the value of the OTP ROM HiCurAcpModeEn bit.
3:2 Reserved RW Reserved. These registers are unused and returns whatever value was written.
1 autoModeEnz RW Automatic Mode Enable. This bit is loaded at the de-assertion of reset with the value of the AUTOENz/HS_SUSPEND pin.
The automatic mode only applies to downstream ports with battery charging enabled when the upstream port is not connected. Under these conditions:
0 = Automatic mode battery charging features are enabled.
1 = Automatic mode is disabled; only Battery Charging DCP and CDP mode is supported.
NOTE: When the upstream port is connected, Battery Charging CDP mode is supported on all ports that are enabled for battery charging support regardless of the value of this bit.
0 RSVD RO Reserved. Read only, returns 0 when read.