SLLSF93 June 2019 TUSB8042A
PRODUCTION DATA.
Bit No. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 0 | 1 | X | X | 0 | 0 |
Bit | Field | Type | Description |
---|---|---|---|
7 | customStrings | RW | Custom strings enable. This bit controls the ability to write to the Manufacturer String Length, Manufacturer String, Product String Length, Product String, and Language ID registers
0 = The Manufacturer String Length, Manufacturer String, Product String Length, Product String, and Language ID registers are read only 1 = The Manufacturer String Length, Manufacturer String, Product String Length, Product String, and Language ID registers may be loaded by EEPROM or written by SMBus The default value of this bit is 0. |
6 | customSernum | RW | Custom serial number enable. This bit controls the ability to write to the serial number registers.
0 = The Serial Number String Length and Serial Number String registers are read only 1 = Serial Number String Length and Serial Number String registers may be loaded by EEPROM or written by SMBus The default value of this bit is 0. |
5 | u1u2Disable | RW | U1 U2 Disable. This bit controls the U1/U2 support.
0 = U1/U2 support is enabled 1 = U1/U2 support is disabled, the TUSB8042A will not initiate or accept any U1 or U2 requests on any port, upstream or downstream, unless it receives or sends a Force_LinkPM_Accept LMP. After receiving or sending an FLPMA LMP, it continues to enable U1 and U2 according to USB 3.2 protocol until it gets a power-on reset or is disconnected on its upstream port. When the TUSB8042A is in I2C mode, the TUSB8042A loads this bit from the contents of the EEPROM. When the TUSB8042A is in SMBUS mode, the value may be over-written by an SMBus host. |
4 | RSVD | RO | Reserved. This bit is reserved and returns 1 when read. |
3 | ganged | RW | Ganged. This bit is loaded at the de-assertion of reset with the value of the GANGED/SMBA2/HS_UP pin.
0 = When fullPwrMgmtz = 0, each port is individually power switched and enabled by the PWRCTL[4:1]/BATEN[4:1] pins 1 = When fullPwrMgmtz = 0, the power switch control for all ports is ganged and enabled by the PWRCTL[4:1]/BATEN1 pin When the TUSB8042A is in I2C mode, the TUSB8042A loads this bit from the contents of the EEPROM. When the TUSB8042A is in SMBUS mode, the value may be over-written by an SMBus host. |
2 | fullPwrMgmtz | RW | Full Power Management. This bit is loaded at the de-assertion of reset with the value of the FULLPWRMGMTz/SMBA1/SS_UP pin.
0 = Port power switching status reporting is enabled 1 = Port power switching status reporting is disabled When the TUSB8042A is in I2C mode, the TUSB8042A loads this bit from the contents of the EEPROM. When the TUSB8042A is in SMBUS mode, the value may be over-written by an SMBus host. |
1 | u1u2TimerOvr | RW | U1 U2 Timer Override. When this field is set, the TUSB8042A overrides the downstream ports U1/U2 timeout values set by USB 3.2 Host software. If software sets value in the range of 1h - FFh, the TUSB8042A uses the value of FFh. If software sets value to 0, then TUSB8042A uses value of 0. REG_09h [6] must be set to enable this feature. |
0 | RSVD | RO | Reserved. This field is reserved and returns 0 when read. |