SCES650I APRIL   2006  – March 2018 TXB0104

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application Block Diagram for TXB010X
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Assignments: GXU and ZXU Package
    3.     Pin Assignments: YZT Package
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: VCCA = 1.2 V
    7. 6.7  Timing Requirements: VCCA = 1.5 V ± 0.1 V
    8. 6.8  Timing Requirements: VCCA = 1.8 V ± 0.15 V
    9. 6.9  Timing Requirements: VCCA = 2.5 V ± 0.2 V
    10. 6.10 Timing Requirements: VCCA = 3.3 V ± 0.3 V
    11. 6.11 Switching Characteristics: VCCA = 1.2 V
    12. 6.12 Switching Characteristics: VCCA = 1.5 V ± 0.1 V
    13. 6.13 Switching Characteristics: VCCA = 1.8 V ± 0.15 V
    14. 6.14 Switching Characteristics: VCCA = 2.5 V ± 0.2 V
    15. 6.15 Switching Characteristics: VCCA = 3.3 V ± 0.3 V
    16. 6.16 Operating Characteristics: VCCA = 1.2 V to 1.5 V, VCCB = 1.5 V to 1.8 V
    17. 6.17 Operating Characteristics: VCCA = 1.8 V to 3.3 V, VCCB = 1.8 V to 5 V
    18. 6.18 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Architecture
      2. 8.3.2 Input Driver Requirements
      3. 8.3.3 Output Load Considerations
      4. 8.3.4 Enable and Disable
      5. 8.3.5 Pullup or Pulldown Resistors on I/O Lines
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • RGY|14
  • RUT|12
  • YZT|12
  • PW|14
  • ZXU|12
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Output Load Considerations

TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths must be kept short enough such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay on for approximately 10 ns. The maximum capacitance of the lumped load that can be driven also depends directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC, load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the capacitance that the device output sees, so it is recommended that this lumped-load capacitance be considered to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse system-level affects.