SLUS223G April   1997  – July 2022 UC1842 , UC1843 , UC1844 , UC1845 , UC2842 , UC2843 , UC2844 , UC2845 , UC3842 , UC3843 , UC3844 , UC3845

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 VFB
        3. 8.3.1.3 ISENSE
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GROUND
        6. 8.3.1.6 OUTPUT
        7. 8.3.1.7 VCC
        8. 8.3.1.8 VREF
      2. 8.3.2  Pulse-by-Pulse Current Limiting
      3. 8.3.3  Current-Sense
      4. 8.3.4  Error Amplifier With Low Output Resistance
      5. 8.3.5  Undervoltage Lockout
      6. 8.3.6  Oscillator
      7. 8.3.7  Synchronization
      8. 8.3.8  Shutdown Technique
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Soft Start
      11. 8.3.11 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Open-Loop Test Fixture
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Input Bulk Capacitor and Minimum Bulk Voltage
        2. 9.2.2.2  Transformer Turns Ratio and Maximum Duty Cycle
        3. 9.2.2.3  Transformer Inductance and Peak Currents
        4. 9.2.2.4  Output Capacitor
        5. 9.2.2.5  Current Sensing Network
        6. 9.2.2.6  Gate Drive Resistor
        7. 9.2.2.7  VREF Capacitor
        8. 9.2.2.8  RT/CT
        9. 9.2.2.9  Start-Up Circuit
        10. 9.2.2.10 Voltage Feedback Compensation
          1. 9.2.2.10.1 Power Stage Poles and Zeroes
          2. 9.2.2.10.2 Slope Compensation
          3. 9.2.2.10.3 Open-Loop Gain
          4. 9.2.2.10.4 Compensation Loop
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Feedback Traces
      2. 11.1.2 Bypass Capacitors
      3. 11.1.3 Compensation Components
      4. 11.1.4 Traces and Ground Planes
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.2 Transformer Turns Ratio and Maximum Duty Cycle

The transformer design starts with selecting a suitable switching frequency for the given application. The UC2842 is capable of switching up to 500 kHz but considerations such as overall converter size, switching losses, core loss, system compatibility, and interference with communication frequency bands generally determine an optimum frequency that should be used. For this off-line converter, the switching frequency, fSW, is selected to be 110 kHz as a compromise to minimize the transformer size and the EMI filter size, and still have acceptable losses.

The transformer primary to secondary turns ratio, NPS, can be selected based on the desired MOSFET voltage rating and the secondary diode voltage rating. Because the maximum input voltage is 265 VRMS, the peak bulk input voltage can be calculated as shown in Equation 10.

Equation 10. GUID-970F8018-61EC-4927-AEB1-86BDB4A479F6-low.gif

To minimize the cost of the system, a readily available 650-V MOSFET is selected. Derating the maximum voltage stress on the drain to 80% of its rated value and allowing for a leakage inductance voltage spike of up to 30% of the maximum bulk input voltage, the reflected output voltage should be less than 130 V as shown in Equation 11.

Equation 11. GUID-1CA2006A-609D-4551-908E-D3BC3F0CF049-low.gif

The maximum primary to secondary transformer turns ratio, NPS, for a 12 V output can be selected as

Equation 12. GUID-B48A4A33-D032-4483-AB44-FD55FE411BF7-low.gif

A turns ratio of NPS = 10 is used in the design example.

The auxiliary winding is used to supply bias voltage to the UC2842. Maintaining the bias voltage above the VCC minimum operating voltage after turn on is required for stabile operation. The minimum VCC operating voltage for the UC2842 version of the controller is 10 V. The auxiliary winding is selected to support a 12-V bias voltage so that it is above the minimum operating level but still keeps the losses low in the IC. The primary to auxiliary turns ratio, NPA, can be calculated from Equation 13:

Equation 13. GUID-1793E05A-BC7E-46CD-AAE3-B30655B0E30C-low.gif

The output diode experiences a voltage stress that is equal to the output voltage plus the reflected input voltage:

Equation 14. GUID-98912B2A-6EC6-4DD0-98C4-1109F0A8EFAD-low.gif

To allow for voltage spikes due to ringing, a Schottky diode with a rated blocking voltage of greater than 60 V is recommended for this design. The forward voltage drop, VF, of this diode is estimated to be equal to 0.6 V

To avoid high peak currents, the flyback converter in this design operates in continuous conduction mode. Once NPS has been determined, the maximum duty cycle, DMAX, can be calculated using the transfer function for a CCM flyback converter:

Equation 15. GUID-35BEB824-0EED-4DEE-9EAE-53B1FCD750A2-low.gif
Equation 16. GUID-722655BA-F574-48F3-B6C8-910427119299-low.gif

Because the maximum duty cycle exceeds 50%, and the design is an off-line (AC-input) application, the UC2842 is best suited for this application.