SLUS223G April 1997 – July 2022 UC1842 , UC1843 , UC1844 , UC1845 , UC2842 , UC2843 , UC2844 , UC2845 , UC3842 , UC3843 , UC3844 , UC3845
PRODUCTION DATA
The design of the compensation loop involves selecting the appropriate components so that the required gain, poles, and zeros can be designed to result in a stabile system over the entire operating range. There are three distinct portions of the loop: the TL431, the opto-coupler, and the error amplifier. Each of these stages is combined with the power stage to result in a stable robust system.
For good transient response, the bandwidth of the finalized design should be as large as possible. The bandwidth of a CCM flyback, f_{BW}, is limited to ¼ of the RHP zero frequency, or approximately 1.77 kHz using Equation 47.
The gain of the open-loop power stage at f_{BW} can be calculated using Equation 46 or can be observed on the Bode plot (Figure 9-3 ) and is equal to –19.55 dB and the phase at f_{BW} is equal to –58°.
The secondary side portion of the compensation loop begins with establishing the regulated steady state output voltage. To set the regulated output voltage, a TL431 adjustable precision shunt regulator is ideally suited for use on the secondary side of isolated converters due to its accurate voltage reference and internal op amp. The resistors used in the divider from the output terminals of the converter to the TL431 REF pin are selected based upon the desired power consumption. Because the REF input current for the TL431 is only 2 µA, selecting the resistors for a divider current, I_{FB_REF}, of 1 mA results in minimal error. The top divider resistor, R_{FBU}, is calculated using Equation 48:
The TL431 reference voltage, REF_{TL431}, has a typical value of 2.495 V. A 9.53-kΩ resistor is chosen for R_{FBU}. To set the output voltage to 12 V, 2.49 kΩ is used for R_{FBB}.
For good phase margin, a compensator zero, f_{COMPz}, is needed and should be placed at 1/10th the desired bandwidth:
With this converter, f_{COMPz} should be set at approximately 177 Hz. A series resistor, R_{COMPz}, and capacitor, C_{COMPz}, placed across the TL431 cathode to REF sets the compensator zero location. Setting C_{COMPz} to 0.01 µF, R_{COMPz} is calculated using Equation 52:
Using a standard value of 88.7 kΩ for R_{Z} and a 0.01 µF for C_{Z} results in a zero placed at 179 Hz.
Referring to Figure 9-2, R_{TLbias} provides cathode current to the TL431 from the regulated voltage provided from the Zener diode, D_{REG}. For robust performance, 10 mA is provided to bias the TL431 by way of the 10-V Zener and 1-kΩ resistor is used for R_{TLbias}.
The gain of the TL431 portion of the compensation loop can be written as:
A compensation pole is needed at the frequency of right half plane zero or the ESR zero, whichever is lowest. Based previous the analysis, the right half plane zero, f_{RHPz}, is located at 7.07 kHz and the ESR zero, f_{ESRz}, is at 1.68 kHz; therefore, for this design, the compensation pole must be put at 1.68 kHz. The opto-coupler contains a parasitic pole that is difficult to characterize over frequency so the opto-coupler is set up with a pulldown resistor, R_{OPTO} equal to 1 kΩ, which moves the parasitic opto-coupler pole further out and beyond the range of interest for this design.
The required compensation pole can be added to the primary side error amplifier using R_{COMPp} and C_{COMPp}. Choosing R_{COMPp} as 10 kΩ, the required value of C_{COMPp} is determined using Equation 54.
A 10-nF capacitor is used for C_{COMPp} setting the compensation pole at 1.59 kHz.
Adding a DC gain to the primary side error amplifier may be required to obtain the required bandwidth and helps to adjust the loop gain as needed. Using a 4.99 kΩ for R_{FBG} sets the DC gain on the error amplifier to 2. At this point the gain transfer function of the error amplifier stage, G_{EA}(s), of the compensation loop can be characterized:
Using an opto-coupler whose current transfer ratio (CTR) is typically at 100% in the frequency range of interest so that CTR = 1, the transfer function of the opto-coupler stage, G_{OPTO}(s), is equal to:
The bias resistor, R_{LED}, to the internal diode of the opto-coupler, and the pulldown resistor on the opto emitter, R_{OPTO}, sets the gain across the isolation boundary. R_{OPTO} has already been set to 1 kΩ but the value of R_{LED} has not yet been determined.
The total closed-loop gain, G_{TOTAL}(s), is the combination of the open-loop power stage, H_{o}(s), the opto gain, G_{OPTO}(s), the error amplifier gain, G_{EA}(s), and the gain of the TL431 stage, G_{TL431}(s):
The required value for R_{LED} can be selected to achieve the desired crossover frequency, f_{BW}. By setting the total loop gain equal to 1 at the desired crossover frequency and rearranging Equation 57, the optimal value for R_{LED} can be determined, as shown in Equation 58.
A 1.3-kΩ resistor suits the requirement for R_{LED}.
Based on the compensation loop structure, the entire compensation loop transfer function is written as Equation 59.
The final closed-loop bode plots are show in Figure 9-5 and Figure 9-6. The converter achieves a crossover frequency of approximately 1.8 kHz and has a phase margin of approximately 67^{o}.
TI recommends checking the loop stability across all the corner cases including component tolerances to ensure system stability.