SLUS223G April   1997  – July 2022 UC1842 , UC1843 , UC1844 , UC1845 , UC2842 , UC2843 , UC2844 , UC2845 , UC3842 , UC3843 , UC3844 , UC3845

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 VFB
        3. 8.3.1.3 ISENSE
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GROUND
        6. 8.3.1.6 OUTPUT
        7. 8.3.1.7 VCC
        8. 8.3.1.8 VREF
      2. 8.3.2  Pulse-by-Pulse Current Limiting
      3. 8.3.3  Current-Sense
      4. 8.3.4  Error Amplifier With Low Output Resistance
      5. 8.3.5  Undervoltage Lockout
      6. 8.3.6  Oscillator
      7. 8.3.7  Synchronization
      8. 8.3.8  Shutdown Technique
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Soft Start
      11. 8.3.11 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Open-Loop Test Fixture
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Input Bulk Capacitor and Minimum Bulk Voltage
        2. 9.2.2.2  Transformer Turns Ratio and Maximum Duty Cycle
        3. 9.2.2.3  Transformer Inductance and Peak Currents
        4. 9.2.2.4  Output Capacitor
        5. 9.2.2.5  Current Sensing Network
        6. 9.2.2.6  Gate Drive Resistor
        7. 9.2.2.7  VREF Capacitor
        8. 9.2.2.8  RT/CT
        9. 9.2.2.9  Start-Up Circuit
        10. 9.2.2.10 Voltage Feedback Compensation
          1. 9.2.2.10.1 Power Stage Poles and Zeroes
          2. 9.2.2.10.2 Slope Compensation
          3. 9.2.2.10.3 Open-Loop Gain
          4. 9.2.2.10.4 Compensation Loop
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Feedback Traces
      2. 11.1.2 Bypass Capacitors
      3. 11.1.3 Compensation Components
      4. 11.1.4 Traces and Ground Planes
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.5 Undervoltage Lockout

The UCx84x devices feature undervoltage lockout protection circuits for controlled operation during power-up and power-down sequences. The UVLO circuit insures that VCC is adequate to make the UCx84x fully operational before enabling the output stage. Undervoltage lockout thresholds for the UCx842, UCx843, UCx844, and UCx845 devices are optimized for two groups of applications: off-line power supplies and DC-DC converters. The 6-V hysteresis in the UCx842 and UCx844 devices prevents VCC oscillations during power sequencing. This wider VCCON to VCCOFF range, make these devices ideally suited to off-line AC input applications. The UCx843 and UCx845 controllers have a much narrower VCCON to VCCOFF hysteresis and may be used in DC to DC applications where the input is considered regulated.

Start-up current is less than 1 mA for efficient bootstrapping from the rectified input of an off-line converter, as illustrated by Figure 8-7. During normal circuit operation, VCC is developed from auxiliary winding NA with DBIAS and CVCC. At start-up, however, CVCC must be charged to 16 V through RSTART. With a start-up current of 1 mA, RSTART can be as large as 100 kΩ and still charge CVCC when VAC = 90 V RMS (low line). Power dissipation in RSTART would then be less than 350 mW even under high line (VAC= 130 V RMS) conditions.

During UVLO the IC draws less than 1 mA of supply current. Once crossing the turnon threshold the IC supply current increases to a maximum of 17 mA, typically 11 mA, During undervoltage lockout, the output driver is biased to a high impedance state and sinks minor amounts of current. A bleeder resistor, placed between the gate and the source of the MOSFET should be used to prevent activating the power switch with extraneous leakage currents during undervoltage lockout.

GUID-D5A83CF0-E16E-403B-BB11-F0F7F199308C-low.gifFigure 8-5 UVLO Threshold
GUID-9408B1A4-24C2-44B0-BC9E-58C5517A2698-low.gifFigure 8-6 UVLO ON and OFF Profile
GUID-EC97237A-9B7E-42C5-93A6-67EE1506BA97-low.gifFigure 8-7 Providing Power to UCx84x