SLUS223G April   1997  – July 2022 UC1842 , UC1843 , UC1844 , UC1845 , UC2842 , UC2843 , UC2844 , UC2845 , UC3842 , UC3843 , UC3844 , UC3845

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 VFB
        3. 8.3.1.3 ISENSE
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GROUND
        6. 8.3.1.6 OUTPUT
        7. 8.3.1.7 VCC
        8. 8.3.1.8 VREF
      2. 8.3.2  Pulse-by-Pulse Current Limiting
      3. 8.3.3  Current-Sense
      4. 8.3.4  Error Amplifier With Low Output Resistance
      5. 8.3.5  Undervoltage Lockout
      6. 8.3.6  Oscillator
      7. 8.3.7  Synchronization
      8. 8.3.8  Shutdown Technique
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Soft Start
      11. 8.3.11 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Open-Loop Test Fixture
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Input Bulk Capacitor and Minimum Bulk Voltage
        2. 9.2.2.2  Transformer Turns Ratio and Maximum Duty Cycle
        3. 9.2.2.3  Transformer Inductance and Peak Currents
        4. 9.2.2.4  Output Capacitor
        5. 9.2.2.5  Current Sensing Network
        6. 9.2.2.6  Gate Drive Resistor
        7. 9.2.2.7  VREF Capacitor
        8. 9.2.2.8  RT/CT
        9. 9.2.2.9  Start-Up Circuit
        10. 9.2.2.10 Voltage Feedback Compensation
          1. 9.2.2.10.1 Power Stage Poles and Zeroes
          2. 9.2.2.10.2 Slope Compensation
          3. 9.2.2.10.3 Open-Loop Gain
          4. 9.2.2.10.4 Compensation Loop
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Feedback Traces
      2. 11.1.2 Bypass Capacitors
      3. 11.1.3 Compensation Components
      4. 11.1.4 Traces and Ground Planes
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.2.10.2 Slope Compensation

Slope compensation is the large signal sub-harmonic instability that can occur with duty cycles that may extend beyond 50% where the rising primary side inductor current slope may not match the falling secondary side current slope. The sub-harmonic oscillation would result in an increase in the output voltage ripple and may even limit the power handling capability of the converter.

The target of slope compensation is to achieve an ideal quality coefficient, QP , to be equal to 1 at half of the switching frequency. The QP is calculated with Equation 37.

Equation 37. GUID-B7CD0A9F-AA81-40A2-9556-D9D1743F3FDD-low.gif

In Equation 37, D is the primary side switch duty cycle and MC is the slope compensation factor, which is defined with Equation 38.

Equation 38. GUID-F24D8F87-A178-445E-9730-E5EA6EED832F-low.gif

In Equation 38, Se is the compensation ramp slope and the Sn is the inductor rising slope. The optimal goal of the slope compensation is to achieve QP equal to 1; upon rearranging Equation 38 the ideal value of slope compensation factor is determined:

Equation 39. GUID-694E4759-B1D6-4689-9892-8C9F8F3DEE64-low.gif

For this design to have adequate slope compensation, MC must be 2.193 when D reaches it maximum value of 0.627.

The inductor rising slope, Sn, at the ISENSE pin is calculated with Equation 40.

Equation 40. GUID-C84D26B5-7F7D-41FA-BCAB-43B3660B09B9-low.gif

The compensation slope, Se, is calculated with Equation 41.

Equation 41. GUID-961C83BE-84AB-4AB7-AC03-0E62E3297532-low.gif

The compensation slope is added into the system through RRAMP and RCSF. The CRAMP is an AC-coupling capacitor that allows the voltage ramp of the oscillator to be used without adding an offset to the current sense; select a value to approximate high frequency short circuit, such as 10 nF as a starting point and make adjustments if required. The RRAMP and RCSF resistors form a voltage divider from the oscillator charge slope and this proportional ramp is injected into the ISENSE pin to add slope compensation. Choose the value of RRAMP to be much larger than the RRT resistor so that it does not load down the internal oscillator and result in a frequency shift.  The oscillator charge slope is calculated using the peak-to-peak voltage of the RT/CT sawtooth waveform, VOSCpp, equal to 1.7 V, and the minimum on-time, as shown in Equation 43.

Equation 42. GUID-97F3910C-F534-4739-A24D-4AF63893EF34-low.gif
Equation 43. GUID-864EB5AC-7CBC-455C-ADC5-FD0933AFAC9F-low.gif

To achieve a 44.74-mV/µs compensation slope, RCSF resistor is calculated with Equation 44. In this design, RRAMP is selected as 24.9 kΩ, a 4.2-kΩ resistor was selected for RCSF.

Equation 44. GUID-4762B6E0-84B1-46C6-807D-8F4736BCBFBC-low.gif