SLUS224F September 1994 – October 2017 UC1842A , UC1843A , UC1844A , UC1845A , UC2842A , UC2843A , UC2844A , UC2845A , UC3842A , UC3843A , UC3844A , UC3845A

PRODUCTION DATA.

- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

The UCx84xA controllers are peak-current mode pulse-width modulators. These controllers have an onboard amplifier and can be used in isolated or nonisolated power supply designs. There is an onboard totem-pole gate driver capable of delivering 1 A of peak current. This is a high-speed PWM capable of operating at switching frequencies up to 500 kHz.

A typical application for the UC3842A in an off-line flyback converter is shown in Figure 10. The UC3842A uses an inner current control loop that contains a small current sense resistor which senses the primary inductor current ramp. This current sense resistor transforms the inductor current waveform to a voltage signal that is input directly into the primary side PWM comparator. This inner loop determines the response to input voltage changes. An outer voltage control loop involves comparing a portion of the output voltage to a reference voltage at the input of an error amplifier. When used in an off-line isolated application, the voltage feedback of the isolated output is accomplished using a secondary-side error amplifier and adjustable voltage reference, such as the TL431. The error signal crosses the primary to secondary isolation boundary using an opto-isolator whose collector is connected to the VREF pin and the emitter is connected to FB. The outer voltage control loop determines the response to load changes.

For this design example, use the parameters listed in Table 1 as the input parameters.

PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|

INPUT CHARACTERISTICS | |||||

V_{IN} |
Input voltage (RMS) | 85 | 265 | V | |

f_{LINE} |
Line frequency | 47 | 63 | Hz | |

OUTPUT CHARACTERISTICS | |||||

V_{OUT} |
Output voltage | 11.75 | 12 | 12.25 | V |

Output ripple voltage | 50 | mV_{PP} |
|||

I_{OUT} |
Output current | 4 | 4.33 | A | |

Load step | 11.75 | 12.25 | V | ||

SYSTEMS CHARACTERISTICS | |||||

η | Maximum load efficiency | 86% |

Click here to create a custom design using the UCx84xA device with the WEBENCH® Power Designer.

- Start by entering the input voltage (V
_{IN}), output voltage (V_{OUT}), and output current (I_{OUT}) requirements. - Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
- Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

- Run electrical simulations to see important waveforms and circuit performance
- Run thermal simulations to understand board thermal performance
- Export customized schematic and layout into popular CAD formats
- Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

This application design procedure shows how to setup and use the UC2842A peak current mode controller in an offline flyback converter, with universal input to a 12-V, 48-W regulated output.

Setting up and designing with the UC2842A peak current mode controller in a continuous mode flyback application requires knowing some things about the power stage. First, calculate the required input bulk capacitance (C_{IN}) based on output power level (P_{OUT}), efficiency (ƞ), minimum input voltage (V_{IN(min)}), line frequency (f_{LINE}) and minimum bulk voltage. For this design example let V_{BULK(min)} = 95 V.

Equation 2.

Equation 3.

The output capacitor (C_{OUT}) is sized so the output voltage does not droop more than 10% during a large-signal transient response. The voltage-loop crossover frequency (f_{C}) is estimated to be 2.5 kHz at this point in the design.

The C_{OUT} selected for the design is a 2200-µF capacitor, with an equivalent series resistance (ESR) of 45 mΩ.

Next calculate the maximum primary to secondary turns ratio (N_{PS}) of the transformer, based on the minimum input voltage and output voltage.

Equation 5.

Next calculate the auxiliary to secondary turns ratio (N_{AS}) of the transformer, based on the output voltage and the bias voltage of the UC2842A.

Equation 6.

Once the transformer turns ratios have been determined, the minimum primary magnetizing inductance (L_{PM}) of the transformer can be calculated based on minimum bulk voltage, Duty Cycle (D), reflected output current and efficiency. The transformer used in this design has an L_{PM} of 1.7 mH, N_{PS} = 10, and a N_{AS} = 1, f_{sw} = 100 kHz

Equation 7.

After the transformer has been selected, the primary peak current (I_{LpPK}) of the transformer can be calculated based on the primary magnetizing inductance ripple (I_{LPM}) and the reflected output current across the transformer.

Equation 9.

Equation 10.

Once the primary peak current has been calculated the current sense resistor (R_{CS}) can be selected.

Equation 11.

Resistors R_{S1} and R_{S2} are used to set the slope compensation of the design. Capacitor C_{S1} is a DC blocking capacitor, and pull-up resistor R_{P} is used to provide some offset to the current sense signal for noise immunity. R_{P} and R_{S2} were preselected to add a DC offset of 50 mV to the current sense signal.

R_{S1} is selected to set the slope compensation to one-half of the ripple current down slope of the flyback inductor. This can be accomplished by calculating the secondary magnetizing inductance (L_{SM}) and using the following calculation for R_{S1}. The 1.7 V in the R_{S1} equation is the peak-to-peak ripple voltage amplitude of the oscillator.

Equation 12.

where

Resistors R_{I} and R_{K} are selected to the output reference and can be calculated by preselecting a value for R_{K} and knowing the TL431 reference voltage (V_{TL431REF}). After choosing 2.49 kΩ for R_{K}, R_{I} is calculated and a standard resistor value of 9.53 kΩ is chosen for this resistor.

Equation 13.

This design using the UC2842A controller has an interesting control loop with many components. G_{OPTO}(f) is the approximate transfer function across the opto isolator in the design. The pole frequency of the opto isolator is represented by f_{P}. The opto isolator used in this design has a current transfer ratio of 1 and pole frequency of roughly 5 kHz. See Figure 10 for component placement and node voltages. The voltage loop (f_{C}) must cross-over less than the opto isolator pole for simplified compensation.

Equation 14.

Equation 15.

Equation 16.

G_{BC}(f) is an estimate of the transfer function from the output of the opto isolator to the PWM’s control voltage.

Equation 17.

The duty cycle varies with the bulk input voltage (V_{BULK}). V_{BULK} varies from 95 V to 375 V during normal operation. This causes the duty cycle to vary from 24% to 56%.

Equation 18.

G_{CO}(f) is an estimate of the control (V_{C}) to output transfer function, where variable Q is the quality factor.

Equation 19.

The quality factor (Q) is defined by the primary magnetizing inductance change in voltage (S_{N}) as a function of duty cycle; as well as, the added slope compensation (S_{E}).

Equation 20.

Equation 21.

Equation 22.

To ensure that the voltage loop is stable, the crossover frequency must be less than one half of the right-half-plane zero frequency (f_{RHPZ}) of the flyback converter. The right-half-plane zero frequency at the minimum bulk voltage would be roughly 9.8 kHz. For this design example the target crossover of the voltage loop is at 1 kHz. The actual f_{C} may be higher or lower than the target.

Equation 24.

The DC gain of G_{CO}(f) moves with the bulk input voltage. Resistor R_{Z} is selected to crossover the voltage loop when input to the converter is at V_{BULK(min)} and to crossover at 1/5th the maximum crossover frequency.

Equation 25.

Capacitor C_{Z} is selected to add 45° of phase margin at voltage loop crossover. For this design example a 6.8-nF capacitor was used.

Equation 26.

Capacitor C_{P} is selected to attenuate the high frequency gain of the control loop.

Equation 27.

G_{C}(f) is the estimated transfer function of the TL431 compensation.

Equation 28.

T_{V}(f) is the estimated theoretical transfer function of the close-loop gain of the system. The feedback loop response may be different in the actual circuit and may have to be adjusted with a network analyzer to meet actual circuit performance and reliability. The feedback loop response must be evaluated over worse case variations in design parameters.

Equation 29.

For this application example, this design technique generated a theoretical feedback loop (T_{V}(f)) crossover at 1 kHz with roughly 55° of phase margin at a minimum input bulk voltage of 95 V. The theoretical voltage loop at high-line crossed over at 2.7 kHz with a phase margin of 72°. See Figure 11 and Figure 12. T_{V}(f) must be evaluated with a network analyzer and adjust the loop compensation as necessary based on the actual circuitry behavior. Also conduct transient testing to ensure that the device remains stable.

V_{BULK} = 95 V |

V_{BULK} = 375 V |