SLUS224F September   1994  – October 2017 UC1842A , UC1843A , UC1844A , UC1845A , UC2842A , UC2843A , UC2844A , UC2845A , UC3842A , UC3843A , UC3844A , UC3845A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pulse-by-Pulse Current Limiting
      2. 7.3.2 Current Sense Circuit
      3. 7.3.3 Error Amplifier Configuration
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Oscillator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Undervoltage Lockout (UVLO) Start-Up
      3. 7.4.3 UVLO Turnoff Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 UC2842A Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The UCx84xA controllers are peak-current mode pulse-width modulators. These controllers have an onboard amplifier and can be used in isolated or nonisolated power supply designs. There is an onboard totem-pole gate driver capable of delivering 1 A of peak current. This is a high-speed PWM capable of operating at switching frequencies up to 500 kHz.

Typical Application

A typical application for the UC3842A in an off-line flyback converter is shown in Figure 10. The UC3842A uses an inner current control loop that contains a small current sense resistor which senses the primary inductor current ramp.  This current sense resistor transforms the inductor current waveform to a voltage signal that is input directly into the primary side PWM comparator.  This inner loop determines the response to input voltage changes.  An outer voltage control loop involves comparing a portion of the output voltage to a reference voltage at the input of an error amplifier.  When used in an off-line isolated application, the voltage feedback of the isolated output is accomplished using a secondary-side error amplifier and adjustable voltage reference, such as the TL431. The error signal crosses the primary to secondary isolation boundary using an opto-isolator whose collector is connected to the VREF pin and the emitter is connected to FB.  The outer voltage control loop determines the response to load changes.

UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A applications_circuit.gif Figure 10. Typical Flyback Application Circuit

Design Requirements

For this design example, use the parameters listed in Table 1 as the input parameters.

Table 1. Design Parameters

PARAMETER MIN TYP MAX UNIT
INPUT CHARACTERISTICS
VIN Input voltage (RMS) 85 265 V
fLINE Line frequency 47 63 Hz
OUTPUT CHARACTERISTICS
VOUT Output voltage 11.75 12 12.25 V
Output ripple voltage 50 mVPP
IOUT Output current 4 4.33 A
Load step 11.75 12.25 V
SYSTEMS CHARACTERISTICS
η Maximum load efficiency 86%

Detailed Design Procedure

Custom Design With WEBENCH® Tools

Click here to create a custom design using the UCx84xA device with the WEBENCH® Power Designer.

  1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
  2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
  3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

  • Run electrical simulations to see important waveforms and circuit performance
  • Run thermal simulations to understand board thermal performance
  • Export customized schematic and layout into popular CAD formats
  • Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

UC2842A Design Procedure

This application design procedure shows how to setup and use the UC2842A peak current mode controller in an offline flyback converter, with universal input to a 12-V, 48-W regulated output.

Setting up and designing with the UC2842A peak current mode controller in a continuous mode flyback application requires knowing some things about the power stage. First, calculate the required input bulk capacitance (CIN) based on output power level (POUT), efficiency (ƞ), minimum input voltage (VIN(min)), line frequency (fLINE) and minimum bulk voltage. For this design example let VBULK(min) = 95 V.

Equation 2. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_vinripple.gif
Equation 3. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_cin.gif

The output capacitor (COUT) is sized so the output voltage does not droop more than 10% during a large-signal transient response. The voltage-loop crossover frequency (fC) is estimated to be 2.5 kHz at this point in the design.

Equation 4. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_cout.gif

The COUT selected for the design is a 2200-µF capacitor, with an equivalent series resistance (ESR) of 45 mΩ.

Next calculate the maximum primary to secondary turns ratio (NPS) of the transformer, based on the minimum input voltage and output voltage.

Equation 5. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_nps.gif

Next calculate the auxiliary to secondary turns ratio (NAS) of the transformer, based on the output voltage and the bias voltage of the UC2842A.

Equation 6. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_nas.gif

Once the transformer turns ratios have been determined, the minimum primary magnetizing inductance (LPM) of the transformer can be calculated based on minimum bulk voltage, Duty Cycle (D), reflected output current and efficiency. The transformer used in this design has an LPM of 1.7 mH, NPS = 10, and a NAS = 1, fsw = 100 kHz

Equation 7. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_d.gif
Equation 8. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_lpm.gif

After the transformer has been selected, the primary peak current (ILpPK) of the transformer can be calculated based on the primary magnetizing inductance ripple (ILPM) and the reflected output current across the transformer.

Equation 9. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_ilpm.gif
Equation 10. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_Ilppk.gif

Once the primary peak current has been calculated the current sense resistor (RCS) can be selected.

Equation 11. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_rcs.gif

Resistors RS1 and RS2 are used to set the slope compensation of the design. Capacitor CS1 is a DC blocking capacitor, and pull-up resistor RP is used to provide some offset to the current sense signal for noise immunity. RP and RS2 were preselected to add a DC offset of 50 mV to the current sense signal.

RS1 is selected to set the slope compensation to one-half of the ripple current down slope of the flyback inductor. This can be accomplished by calculating the secondary magnetizing inductance (LSM) and using the following calculation for RS1. The 1.7 V in the RS1 equation is the peak-to-peak ripple voltage amplitude of the oscillator.

Equation 12. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_rs1.gif

where

  • UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_rs2.gif

Resistors RI and RK are selected to the output reference and can be calculated by preselecting a value for RK and knowing the TL431 reference voltage (VTL431REF). After choosing 2.49 kΩ for RK, RI is calculated and a standard resistor value of 9.53 kΩ is chosen for this resistor.

Equation 13. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_ri.gif

This design using the UC2842A controller has an interesting control loop with many components. GOPTO(f) is the approximate transfer function across the opto isolator in the design. The pole frequency of the opto isolator is represented by fP. The opto isolator used in this design has a current transfer ratio of 1 and pole frequency of roughly 5 kHz. See Figure 10 for component placement and node voltages. The voltage loop (fC) must cross-over less than the opto isolator pole for simplified compensation.

Equation 14. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_s(f).gif
Equation 15. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_fp.gif
Equation 16. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_gopto.gif

GBC(f) is an estimate of the transfer function from the output of the opto isolator to the PWM’s control voltage.

Equation 17. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_Gbc.gif

The duty cycle varies with the bulk input voltage (VBULK). VBULK varies from 95 V to 375 V during normal operation. This causes the duty cycle to vary from 24% to 56%.

Equation 18. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_d2.gif

GCO(f) is an estimate of the control (VC) to output transfer function, where variable Q is the quality factor.

Equation 19. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_gcof.gif

The quality factor (Q) is defined by the primary magnetizing inductance change in voltage (SN) as a function of duty cycle; as well as, the added slope compensation (SE).

Equation 20. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_Sn.gif
Equation 21. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_Se.gif
Equation 22. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_Q.gif

To ensure that the voltage loop is stable, the crossover frequency must be less than one half of the right-half-plane zero frequency (fRHPZ) of the flyback converter. The right-half-plane zero frequency at the minimum bulk voltage would be roughly 9.8 kHz. For this design example the target crossover of the voltage loop is at 1 kHz. The actual fC may be higher or lower than the target.

Equation 23. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_rhpz.gif
Equation 24. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_fc2.gif

The DC gain of GCO(f) moves with the bulk input voltage. Resistor RZ is selected to crossover the voltage loop when input to the converter is at VBULK(min) and to crossover at 1/5th the maximum crossover frequency.

Equation 25. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_rz.gif

Capacitor CZ is selected to add 45° of phase margin at voltage loop crossover. For this design example a 6.8-nF capacitor was used.

Equation 26. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_cz.gif

Capacitor CP is selected to attenuate the high frequency gain of the control loop.

Equation 27. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_cp.gif

GC(f) is the estimated transfer function of the TL431 compensation.

Equation 28. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_gc.gif

TV(f) is the estimated theoretical transfer function of the close-loop gain of the system. The feedback loop response may be different in the actual circuit and may have to be adjusted with a network analyzer to meet actual circuit performance and reliability. The feedback loop response must be evaluated over worse case variations in design parameters.

Equation 29. UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A eq_tv(f).gif

For this application example, this design technique generated a theoretical feedback loop (TV(f)) crossover at 1 kHz with roughly 55° of phase margin at a minimum input bulk voltage of 95 V. The theoretical voltage loop at high-line crossed over at 2.7 kHz with a phase margin of 72°. See Figure 11 and Figure 12. TV(f) must be evaluated with a network analyzer and adjust the loop compensation as necessary based on the actual circuitry behavior. Also conduct transient testing to ensure that the device remains stable.

Application Curves

UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A loop_gain_95V.gif
VBULK = 95 V
Figure 11. Voltage Loop Gain
UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A startup.gif Figure 13. VOUT Start-Up Full Load
UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A loop_gain_375V.gif
VBULK = 375 V
Figure 12. Voltage Loop Gain
UC1842A UC1843A UC1844A UC1845A UC2842A UC2843A UC2844A UC2845A UC3842A UC3843A UC3844A UC3845A voutripple.gif Figure 14. VOUT Ripple Voltage