SLUSE80A September   2021  – November 2021 UCC14240-Q1

ADVANCE INFORMATION  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Power Ratings
    6. 6.6 Insulation Specifications
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
      2. 7.3.2 Digital I/O ENA and /PG
      3. 7.3.3 Power-Up and Power-Down Sequencing
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 RLIM Resistor Selection
        2. 8.2.2.2 Capacitor Selection
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • DWN|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Device Functional Modes

Table 7-1 lists the supply functional modes for this device. The ENA pin has an internal weak pull-down resistance to ground, but leaving this pin open is not recommended

Table 7-1 Device Functional Modes

INPUT

OUTPUTS
VVIN ENA FAULT V(VDD – VEE)
Isolated Output1		 V(COM – VEE)
Isolated Output2		 /PG Open Drain
VVIN < UVLOp X X OFF OFF HIGH
UVLOp < VVIN < OVLOp LOW X OFF OFF HIGH
UVLOp < VVIN < OVLOp HIGH NO FAULT Regulating at Setpoint Regulating at Setpoint LOW
UVLOp < VVIN < OVLOp HIGH YES FAULT OFF OFF HIGH
VVIN > OVLOp X X OFF OFF HIGH