SLUSE80A September   2021  – November 2021 UCC14240-Q1

ADVANCE INFORMATION  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Power Ratings
    6. 6.6 Insulation Specifications
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
      2. 7.3.2 Digital I/O ENA and /PG
      3. 7.3.3 Power-Up and Power-Down Sequencing
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 RLIM Resistor Selection
        2. 8.2.2.2 Capacitor Selection
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • DWN|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.2 Layout Example

The layout example shown in the following figures is from the evaluation board UCC14240EVM-052 and based on the Figure 8-1 design.

The component selection is as follows:

  • CIN = 0.1 μF (0603) + 2.2 μF (0805)
  • COUT1 = 0.1 μF (0603) + 2.2 μF (0805)
  • COUT2 = 0.1 μF (0603) + 2.2 μF (0805)
  • COUT3 = 0.1 μF (0603) + 3 × 3.3 μF (0805)
  • RRLIM = 1 kΩ (0805)

GUID-20210720-CA0I-N3P4-QJZ4-HSBTLX8GMK4R-low.gif

Figure 10-1 UCC14240EVM-052, PCB Top Layer, Assembly

GUID-20210720-CA0I-1NBG-1ML2-0MXJS7Q7HJGR-low.gif

Figure 10-2 UCC14240EVM-052, Signal Layer 2 (Same as Layer 3)

GUID-20210720-CA0I-1NBG-1ML2-0MXJS7Q7HJGR-low.gif

Figure 10-3 UCC14240EVM-052, Signal Layer 3 (Same as Layer 2)

GUID-20210720-CA0I-3CXG-D2QV-BDQCJ1PP1NZW-low.gif

Figure 10-4 UCC14240EVM-052, PCB Bottom Layer, Assembly (Mirrored View)