SLUSE80A September   2021  – November 2021 UCC14240-Q1

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Power Ratings
    6. 6.6 Insulation Specifications
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
      2. 7.3.2 Digital I/O ENA and /PG
      3. 7.3.3 Power-Up and Power-Down Sequencing
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 RLIM Resistor Selection
        2. 8.2.2.2 Capacitor Selection
    3. 8.3 System Examples
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • DWN|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

Over operating temperature range ( = –40 °C ≤ TJ ≤ 150 °C, 21 V ≤ VIN ≤ 27 V, CIN = COUT = 2.2 µF, VENA = 5 V, RLIM = 1 kΩ unless otherwise noted. All typical values at TA = 25 °C and VIN = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY (Primary-side. All voltages with respect to GNDP)
VVIN

Input voltage range

Primary-side input voltage to GNDP

21

24

27

V

IVINQ_OFF VIN quiescent current,disabled ENA = 0 V, VIN = 21 V–27 V; IOUT = no load 500 µA
IVIN_ON_NO_LOAD VIN operating current, no load

ENA = 5 V; VIN = 21 V–27 V; (VDD – VEE) regulating; I((VDD – VEE)) = no load

8

mA
IVIN_ON_FULL_LOAD VIN operating current, full load ENA = 5 V; VIN = 21 V–27 V; (VDD – VEE) = 25-V regulating; I((VDD – VEE)) = 60 mA

135

mA
UVLOP COMPARATOR (Primary-side. All voltages with respect to GNDP)
VVIN_UVLOP_RISING VIN under-voltage lockout rising threshold Voltage at VIN pin while VIN rising 20 V
VVIN_UVLOP_FALLING VIN under-voltage lockout falling threshold Voltage at VIN pin while VIN falling

18

V
OVLOP COMPARATOR (Primary-side. All voltages with respect to GNDP)
VVIN_OVLO_RISING VIN over-voltage lockout rising threshold Voltage at VIN pin while VIN rising

31

V
VVIN_OVLO_FALLING VIN over-voltage lockout falling threshold Voltage at VIN pin while VIN falling

29

V
TSHUTP THERMAL SHUTDOWN COMPARATOR (Primary-side. All voltages with respect to GNDP)
TSHUTPPRIMARY_RISE Primary-side over-temperature shutdown rising threshold First time at power-up Tj needs to be < 140 °C to turn-on.

150

160 °C
TSHUTPPRIMARY_HYST Primary-side over-temperature shutdown hysteresis 20 °C
EN INPUT PIN (Primary-side. All voltages with respect to GNDP)
VEN_IR Input voltage rising threshold, logic HIGH Rising edge 2.1 V
VEN_IF Input voltage falling threshold, logic LOW Falling edge 0.8 V
IEN Enable Pin Input Current VEN = 5.0 V 5 10 µA

/PG OPEN-DRAIN OUTPUT PIN (Primary-side. All voltages with respect to GNDP) [/PG is Active Low ]

V/PG_OUT_LO

/PG output-low

saturation voltage
Sink Current = 5 mA, power is good 0.5 V
I/PG_OUT_HI /PG Leakage current /PG = 5.5 V, power is not good 5 µA
SWITCHING FREQUENCY (Primary-side. All voltages with respect to GNDP)
FSW_CARRIER Switching frequency

range

ENA = 5 V; (VDD – VEE) = 25 V

11

13

17

MHz
VDD OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE)
VVDD_RANGE (VDD - VEE) Output voltage range Secondary-side (VDD – VEE), adjust with external resistor divider 18 22 25 V
VVDD_DC_ACCURACY (VDD - VEE) Output voltage DC regulation accuracy

Secondary-side (VDD – VEE) over load, line and temperature; externally adjust with external resistor divider

-1.3 1.3 %
VDD REGULATION HYSTERETIC COMPARATOR (Secondary-side. All voltages with respect to VEE)
VFBVDD_REF Feedback regulation reference voltage for (VDD - VEE) During secondary soft-start, the (VDD – VEE) reference is stepped-up 2.5 V
VEE OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE)
VVEE_RANGE (COM - VEE) Output voltage range Secondary-side (COM – VEE), adjust with external resistor divider 2.5

5

(VDD-VEE) V
V(VDD-VEE)_DC_ACCURACY (VDD - VEE) Output voltage DC regulation accuracy

Secondary-side VDD output voltage to VEE over load, line and temperature; externally adjust with external resistor divider

-1.3 1.3 %
VEE REGULATION HYSTERETIC COMPARATOR (Secondary-side. All voltages with respect to VEE)
VFBVEE_REF Feedback regulation reference voltage for (COM - VEE) During secondary soft-start, the (COM – VEE) reference is stepped-up same as (VDD – VEE) reference 2.5 V
UVLOS COMPARATOR (Secondary-side. All voltages with respect to VEE)
VVDD_UVLO_RISING (VDD - VEE) under-voltage lockout rising threshold Voltage at FBVDD, using an external resistor divider from VDD to VEE, midpoint connected to FBVDD. 0.9 V
VVDD_UVLO_HYST (VDD - VEE) under-voltage lockout hysteresis Voltage at FBVDD, using an external resistor divider from VDD to VEE, midpoint connected to FBVDD. 0.2 V
tVDD_UVLO_DEGLITCH (VDD - VEE) under-voltage lockout deglitch time Voltage at FBVDD, using an external resistor divider from VDD to VEE, midpoint connected to FBVDD. 2.5 µs
OVLOS COMPARATOR (Secondary-side. All voltages with respect to VEE)
VVDD_OVLOS_RISING (VDD - VEE) over-voltage lockout rising threshold Voltage from VDD to VEE

31

V
VVDD_OVLOS_FALLING (VDD - VEE) over-voltage lockout falling threshold Voltage from VDD to VEE

29

V
tVDD_OVLOS_DEGLITCH (VDD - VEE) over-voltage lockout deglitch time 32 µs
SOFT-START (Secondary-side. All voltages with respect to VEE)
VREF_Voltage_per_Steps Voltage per step 8 Steps start from 1.1 V and end at 2.5 V. That is, 200 mV per step. 0.2 V
VREF_Voltage_Start VREF voltage at Start of secondary-side soft-start 8 Steps start from 1.1 V and end at 2.5 V. That is, 200 mV per step. 1.1 V
VREF_Voltage_End VREF voltage at End of secondary-side soft-start 8 Steps start from 1.1 V and end at 2.5 V. That is, 200 mV per step. 2.5 V
tduration Time duration per step, until get to the last one 128 µs
UVP1, UNDER -VOLTAGE PROTECTION COMPARATOR VDD OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE)
VVDD_UVP_RISING (VDD – VEE) under-voltage protection rising threshold VUVP = VREF × 90% 2.25 V
VVDD_UVP_HYST (VDD – VEE) under-voltage protection hysteresis 25 mV
tVDD_UVP_DEGLITCH (VDD – VEE) under-voltage protection deglitch time 32 µs
tVDD_UVP_FAULT_DEGLITCH (VDD – VEE) under-voltage protection fault latch-off deglitch time 64 µs
OVP1, OVER-VOLTAGE PROTECTION COMPARATOR VDD OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE)
VVDD_OVP_RISING (VDD – VEE) over-voltage protection rising threshold VOVP = VREF × 110% 2.75 V
VVDD_OVP_HYST (VDD – VEE) over-voltage protection hysteresis 25 mV
tVDD_OVP_DEGLITCH (VDD – VEE) over-voltage protection deglitch time 32 µs
tVDD_OVP_FAULT_DEGLITCH (VDD – VEE) over-voltage protection fault latch-off deglitch time 64 µs
UVP2, UNDER -VOLTAGE PROTECTION COMPARATOR (COM – VEE) OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE)
VVEE_UVP_RISING (COM – VEE) under-voltage protection rising threshold VUVP = VREF × 90% 2.25 V
VVEE_UVP_HYST (COM – VEE) under-voltage protection hysteresis 25 mV
tVEE_UVP_DEGLITCH (COM – VEE) under-voltage protection deglitch time 32 µs
tVEE_UVP_FAULT_DEGLITCH (COM – VEE) under-voltage protection fault latch-off deglitch time Fault is communicated to primary at any time to protect and enter a safe state. 64 µs
OVP2, OVER-VOLTAGE PROTECTION COMPARATOR (COM – VEE) OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE)
VVEE_OVP_RISING (COM – VEE) over-voltage protection rising threshold VOVP = VREF × 110% 2.75 V
VVEE_OVP_HYST (COM – VEE) over-voltage protection hysteresis 25 mV
tVEE_OVP_DEGLITCH (COM – VEE) over-voltage protection deglitch time 32 µs
tVEE_OVP_FAULT_DEGLITCH (COM – VEE) over-voltage protection fault latch-off deglitch time Fault is communicated to primary at any time to protect and enter a safe state. 64 µs
TSHUTS THERMAL SHUTDOWN COMPARATOR (Secondary-side. All voltages with respect to VEE)
TSHUTSSECONDARY_RISE Secondary-side over-temperature shutdown rising threshold First time at power-up TJ needs to be < 140 °C to turn-on.

150

160 °C
TSHUTSSECONDARY_HYST Secondary-side over-temperature shutdown hysteresis 20 °C
tTSHUTS_DEGLITCH Secondary-side over-temp shutdown deglitch time. Rising and falling deglitch times 64 µs
WATCHDOG TIMEOUT (Primary-side. All voltages with respect to VEE)
tWATHCHDOG_TIMEOUT Primary-side Watchdog shutdown timeout time Counts while no communication through isolation channel. Communication resets timer. 100 µs
HEARTBEAT TIMEOUT (Secondary-side. All voltages with respect to VEE)
tHEARTBEAT_TIMEOUT Secondary-side heartbeat interval time - reports Power is Good, Power is Not Good, or FAULT Fixed time to reset WDT if active and okay, but no communication change needed. 30 µs
CMTI (Common Mode Transient Immunity)
CMTI Common mode transient immunity Positive VEE with respect to GNDP 150 µs
Negative VEE with respect to GNDP | –150 | µs
INTEGRATED TRANSFORMER (Primary-side to Secondary-side.)
NPRIMARY_TO_SECONDARY Effective turns ratio 1.2 -