SLUSCV6A April 2017 – February 2018 UCC21225A
The recommended input supply voltage (VCCI) for UCC21225A is between 3 V and 18 V. The lower end of the output bias supply voltage (VDDA/VDDB) range is governed by the internal under voltage lockout (UVLO) protection feature of the device. VDD and VCCI should not fall below their respective UVLO thresholds for normal operation, or else gate driver outputs can become clamped low for >50µs by the UVLO protection feature. (For more information on UVLO see VDD, VCCI, and Under Voltage Lock Out (UVLO)). The upper end of the VDDA/VDDB range depends on the maximum gate voltage of the power device being driven by UCC21225A, and should not exceed the recommended maximum VDDA/VDDB of 25-V.
A local bypass capacitor should be placed between the VDD and VSS pins, with a value of between 220 nF and 10 µF for device biasing. It is further suggested that an additional 100-nF capacitor be placed in parallel with the device biasing capacitor for high frequency filtering. Both capacitors should be positioned as close to the device as possible. Low ESR, ceramic surface mount capacitors are recommended.
Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of current drawn by the logic circuitry within the input side of UCC21225A, this bypass capacitor has a minimum recommended value of 100 nF.