SLUSCV6A April 2017 – February 2018 UCC21225A
Before the driver is ready to deliver a proper output state, there is a power-up delay from the UVLO rising edge to output and it is defined as tVCCI+ to OUT for VCCI UVLO (typically 40-µs) and tVDD+ to OUT for VDD UVLO (typically 50-µs). It is recommended to consider proper margin before launching PWM signal after the driver's VCCI and VDD bias supply is ready. Figure 28 and Figure 29 show the power-up UVLO delay timing diagram for VCCI and VDD.
If INA or INB are active before VCCI or VDD have crossed above their respective on thresholds, the output will not update until tVCCI+ to OUT or tVDD+ to OUT after VCCI or VDD crossing its UVLO rising threshold. However, when either VCCI or VDD receive a voltage less than their respective off thresholds, there is <1-µs delay, depending on the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay is designed to ensure safe operation during VCCI or VDD brownouts.