SLUSCQ2D October 2017 – June 2020 UCC21520-Q1
PRODUCTION DATA.
Figure 44 shows a 2-layer PCB layout example with the signals and key components labeled.
Figure 45 and Figure 46 shows top and bottom layer traces and copper.
NOTE
There are no PCB traces or copper between the primary and secondary side, which ensures isolation performance.
PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.
Figure 47 and Figure 48 are 3D layout pictures with top view and bottom views.
NOTE
The location of the PCB cutout between the primary side and secondary sides, which ensures isolation performance.