SLUSCJ9E June   2016  – December 2021 UCC21520

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety-Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Propagation Delay and Pulse Width Distortion
    2. 8.2 Rising and Falling Time
    3. 8.3 Input and Disable Response Time
    4. 8.4 Programable Dead Time
    5. 8.5 Power-up UVLO Delay to OUTPUT
    6. 8.6 CMTI Testing
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)
      2. 9.3.2 Input and Output Logic Table
      3. 9.3.3 Input Stage
      4. 9.3.4 Output Stage
      5. 9.3.5 Diode Structure in the UCC21520 and the UCC21520A
    4. 9.4 Device Functional Modes
      1. 9.4.1 Disable Pin
      2. 9.4.2 Programmable Dead-Time (DT) Pin
        1. 9.4.2.1 Tying the DT Pin to VCC
        2. 9.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins
        3. 9.4.2.3 41
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Designing INA/INB Input Filter
        2. 10.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 10.2.2.3 Gate Driver Output Resistor
        4. 10.2.2.4 Gate to Source Resistor Selection
        5. 10.2.2.5 Estimate Gate Driver Power Loss
        6. 10.2.2.6 Estimating Junction Temperature
        7. 10.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 10.2.2.7.1 Selecting a VCCI Capacitor
          2. 10.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 10.2.2.7.3 Select a VDDB Capacitor
        8. 10.2.2.8 Dead Time Setting Guidelines
        9. 10.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Certifications
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 Support Resources
    6. 13.6 Trademarks
    7. 13.7 Electrostatic Discharge Caution
    8. 13.8 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)

The UCC21520 and the UCC21520A have an internal undervoltage lock out (UVLO) protection feature on the supply circuit blocks between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than VVDD_ON at device start-up or lower than VVDD_OFF after start-up, the VDD UVLO feature holds the effected output low, regardless of the status of the input pins (INA and INB).

When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an active clamp circuit that limits the voltage rise on the driver outputs (Illustrated in Figure 9-1 ). In this condition, the upper PMOS is resistively held off by RHi-Z while the lower NMOS gate is tied to the driver output through RCLAMP. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device, typically around 1.5 V, when no bias power is available.

GUID-0F176833-009C-4BA2-9E90-75BA88FD09B6-low.gifFigure 9-1 Simplified Representation of Active Pulldown Feature

The VDD UVLO protection has a hysteresis feature (VVDD_HYS). This hysteresis prevents chatter when there is ground noise from the power supply. Also this allows the device to accept small drops in bias voltage, which is bound to happen when the device starts switching and operating current consumption increases suddenly.

The input side of the UCC21520 and the UCC21520A also has an internal undervoltage lock out (UVLO) protection feature. The device isn't active unless the voltage, VCCI, is going to exceed VVCCI_ON on start up. And a signal will cease to be delivered when that pin receives a voltage less than VVCCI_OFF. And, just like the UVLO for VDD, there is hysteresis (VVCCI_HYS) to ensure stable operation.

All versions of the UCC21520 can withstand an absolute maximum of 30 V for VDD, and 20 V for VCCI.

Table 9-1 UCC21520 and UCC21520A VCCI UVLO Feature Logic
CONDITIONINPUTSOUTPUTS
INAINBOUTAOUTB
VCCI-GND < VVCCI_ON during device start upHLLL
VCCI-GND < VVCCI_ON during device start upLHLL
VCCI-GND < VVCCI_ON during device start upHHLL
VCCI-GND < VVCCI_ON during device start upLLLL
VCCI-GND < VVCCI_OFF after device start upHLLL
VCCI-GND < VVCCI_OFF after device start upLHLL
VCCI-GND < VVCCI_OFF after device start upHHLL
VCCI-GND < VVCCI_OFF after device start upLLLL
Table 9-2 UCC21520 and UCC21520A VDD UVLO Feature Logic
CONDITIONINPUTSOUTPUTS
INAINBOUTAOUTB
VDD-VSS < VVDD_ON during device start upHLLL
VDD-VSS < VVDD_ON during device start upLHLL
VDD-VSS < VVDD_ON during device start upHHLL
VDD-VSS < VVDD_ON during device start upLLLL
VDD-VSS < VVDD_OFF after device start upHLLL
VDD-VSS < VVDD_OFF after device start upLHLL
VDD-VSS < VVDD_OFF after device start upHHLL
VDD-VSS < VVDD_OFF after device start upLLLL