SLUSDG3D Data sheet

SLUSDG3D August 2018 – April 2021 UCC21530-Q1

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

DWK|14
- MPCS001

Thermal pad, mechanical data (Package|Pins)

Orderable Information

slusdg3d_oa

6.9 Electrical Characteristics

V_VCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA = V_VDDB = 12V or 15V⁽¹⁾, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, DT pin tied to VCCI, C_L = 0 pF, T_A = –40°C to +125°C, (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY CURRENTS
I_VCCI	VCCI quiescent current	V_INA = 0 V, V_INB = 0 V		1.5	2.0	mA
I_VDDA, I_VDDB	VDDA and VDDB quiescent current	V_INA = 0 V, V_INB = 0 V		1.0	1.8	mA
I_VCCI	VCCI per operating current	(f = 500 kHz) current per channel		2.0		mA
I_VDDA, I_VDDB	VDDA and VDDB operating current	(f = 500 kHz) current per channel, C_OUT = 100 pF, V_VDDA, V_VDDB = 15 V		3.0		mA
VCCI TO GND UNDERVOLTAGE THRESHOLDS
V_{VCCI_ON}	UVLO Rising threshold		2.55	2.7	2.85	V
V_{VCCI_OFF}	UVLO Falling threshold		2.35	2.5	2.65	V
V_{VCCI_HYS}	UVLO Threshold hysteresis			0.2		V
UCC21530B-Q1 VDD to VSS UNDERVOLTAGE THRESHOLDS
V_{VDDA_ON}, V_{VDDB_ON}	UVLO Rising threshold		8	8.5	9	V
V_{VDDA_OFF,} V_{VDDB_OFF}	UVLO Falling threshold		7.5	8	8.5	V
V_{VDDA_HYS,} V_{VDDB_HYS}	UVLO Threshold hysteresis			0.5		V
UCC21530-Q1 VDD TO VSS UNDERVOLTAGE THRESHOLDS
V_{VDDA_ON}, V_{VDDB_ON}	UVLO Rising threshold		12.5	13.5	14.5	V
V_{VDDA_OFF,} V_{VDDB_OFF}	UVLO Falling threshold		11.5	12.5	13.5	V
V_{VDDA_HYS,} V_{VDDB_HYS}	UVLO Threshold hysteresis			1.0		V
INA and INB
V_INAH, V_INBH	Input high threshold voltage		1.6	1.8	2	V
V_INAL, V_INBL	Input low threshold voltage		0.8	1	1.2	V
V_{INA_HYS}, V_{INB_HYS}	Input threshold hysteresis			0.8		V
V_INA, V_INB	Negative transient, ref to GND, 50 ns pulse	Not production tested, bench test only	–5			V
EN THRESHOLDS
V_ENH	Enable high voltage		2.0			V
V_ENL	Enable low voltage				0.8	V
OUTPUT
I_OA+, I_OB+	Peak output source current	C_VDD = 10 µF, C_LOAD = 0.18 µF, f = 1 kHz, bench measurement		4		A
I_OA-, I_OB-	Peak output sink current	C_VDD = 10 µF, C_LOAD = 0.18 µF, f = 1 kHz, bench measurement		6		A
R_OHA, R_OHB	Output resistance at high state	I_OUT = –10 mA, T_A = 25°C, R_OHA, R_OHBdo not represent drive pull-up performance. See t_RISE in Section 6.10 and Section 8.3.4 for details.		5		Ω
R_OLA, R_OLB	Output resistance at low state	I_OUT = 10 mA, T_A = 25°C		0.55		Ω
V_OHA, V_OHB	Output voltage at high state	V_VDDA, V_VDDB = 15 V, I_OUT = –10 mA, T_A = 25°C		14.95		V
V_OLA, V_OLB	Output voltage at low state	V_VDDA, V_VDDB = 15 V, I_OUT = 10 mA, T_A = 25°C		5.5		mV
DEADTIME AND OVERLAP PROGRAMMING
Dead time		DT pin tied to VCCI	Overlap determined by INA INB			-
Dead time		R_DT = 20 kΩ	160	200	240	ns