SLUSDG3D August   2018  – April 2021 UCC21530-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 Input and Enable Response Time
    4. 7.4 Programable Dead Time
    5. 7.5 Power-Up UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC21530-Q1
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 DT Pin Tied to VCC
        2. 8.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Component Placement Considerations
      2. 9.1.2 Grounding Considerations
      3. 9.1.3 High-Voltage Considerations
      4. 9.1.4 Thermal Considerations
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.10 Switching Characteristics

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12V or 15V(1), 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tRISEOutput rise time, 20% to 80% measured pointsCOUT = 1.8 nF 616ns
tFALLOutput fall time, 90% to 10% measured pointsCOUT = 1.8 nF712ns
tPWminMinimum pulse widthOutput off for less than minimum, COUT = 0 pF20ns
tPDHLPropagation delay from INx to OUTx falling edges141930ns
tPDLHPropagation delay from INx to OUTx rising edges141930ns
tPWDPulse width distortion |tPDLH – tPDHL|6ns
tDMPropagation delays matching between VOUTA, VOUTBf = 100 kHz5ns
tVCCI+ to OUTVCCI Power-up Delay Time: UVLO Rise to OUTA, OUTB,
See Figure 7-5		INA or INB tied to VCCI40µs
tVDD+ to OUTVDDA, VDDB Power-up Delay Time: UVLO Rise to OUTA, OUTB
See Figure 7-6		INA or INB tied to VCCI50
|CMH|High-level common-mode transient immunity (See Section 7.6)Slew rate of GND vs. VSSA/B, INA and INB both are tied to GND or VCCI; VCM=1500 V;100V/ns
|CML|Low-level common-mode transient immunity (See Section 7.6)Slew rate of GND vs. VSSA/B, INA and INB both are tied to GND or VCCI; VCM=1500 V;100