SLUSDC0C October   2018  – November 2021 UCC21530

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 Input and Enable Response Time
    4. 7.4 Programable Dead Time
    5. 7.5 Power-Up UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC21530
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 DT Pin Tied to VCC
        2. 8.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing INA/INB Input Filter
        2. 9.2.2.2 Select Dead Time Resistor and Capacitor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Estimate Gate Driver Power Loss
        5. 9.2.2.5 Estimating Junction Temperature
        6. 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.6.1 Selecting a VCCI Capacitor
        7. 9.2.2.7 Other Application Example Circuits
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Component Placement Considerations
      2. 11.1.2 Grounding Considerations
      3. 11.1.3 High-Voltage Considerations
      4. 11.1.4 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Insulation Specifications

PARAMETERTEST CONDITIONSVALUEUNIT
CLRExternal clearance(1)Shortest pin-to-pin distance through air> 8mm
CPGExternal creepage(1)Shortest pin-to-pin distance across the package surface> 8mm
DTIDistance through insulationMinimum internal gap (internal clearance) of the double insulation (2 × 10.5 µm)>21µm
CTIComparative tracking indexDIN EN 60112 (VDE 0303-11); IEC 60112> 600V
Material groupAccording to IEC 60664-1I
Overvoltage category per IEC 60664-1Rated mains voltage ≤ 600 VRMSI-IV
Rated mains voltage ≤ 1000 VRMSI-III
DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01(2)
VIORMMaximum repetitive peak isolation voltageAC voltage (bipolar)2121VPK
VIOWMMaximum working isolation voltageAC voltage (sine wave); time dependent dielectric breakdown (TDDB), test (See Figure 6-1)1500VRMS
DC voltage2121VDC
VIOTMMaximum transient isolation voltageVTEST = VIOTM, t = 60 sec (qualification)
VTEST = 1.2 × VIOTM, t = 1 s (100% production)		8000VPK
VIOSMMaximum surge isolation voltage(3)Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)		8000VPK
qpdApparent charge(4)Method a, After Input/Output safety test subgroup 2/3.
Vini = VIOTM, tini = 60s;

Vpd(m) = 1.2 X VIORM = 2545 VPK, tm = 10s

<5pC
Method a, After environmental tests subgroup 1.
Vini = VIOTM, tini = 60s;

Vpd(m) = 1.6 X VIORM = 3394 VPK, tm = 10s

<5

Method b1; At routine test (100% production) and preconditioning (type test)

Vini = 1.2 × VIOTM; tini = 1s;

Vpd(m) = 1.875 * VIORM = 3977 VPK , tm = 1s

<5
CIOBarrier capacitance, input to output(5)VIO = 0.4 sin (2πft), f =1 MHz1.2pF
RIOIsolation resistance, input to output(5)VIO = 500 V at TA = 25°C> 1012Ω
VIO = 500 V at 100°C ≤ TA ≤ 125°C> 1011
VIO = 500 V at TS =150°C> 109
Pollution degree2
Climatic category40/125/21
UL 1577
VISOWithstand isolation voltageVTEST = VISO = 5700 VRMS, t = 60 sec. (qualification),

VTEST = 1.2 × VISO = 6840VRMS, t = 1 sec (100% production)

5700VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.