SLUSDO2C June   2020  – February 2021 UCC21540-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     UCC21540-Q1 Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety-Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Minimum Pulses
    2. 8.2 Propagation Delay and Pulse Width Distortion
    3. 8.3 Rising and Falling Time
    4. 8.4 Input and Disable Response Time
    5. 8.5 Programmable Dead Time
    6. 8.6 Power-up UVLO Delay to OUTPUT
    7. 8.7 CMTI Testing
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 9.3.2 Input and Output Logic Table
      3. 9.3.3 Input Stage
      4. 9.3.4 Output Stage
      5. 9.3.5 Diode Structure in the UCC21540-Q1
    4. 9.4 Device Functional Modes
      1. 9.4.1 Disable Pin
      2. 9.4.2 Programmable Dead Time (DT) Pin
        1. 9.4.2.1 DT Pin Tied to VCCI
        2. 9.4.2.2 Connecting a Programming Resistor between DT and GND Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Designing INA/INB Input Filter
        2. 10.2.2.2 Select Dead Time Resistor and Capacitor
        3. 10.2.2.3 Select External Bootstrap Diode and its Series Resistor
        4. 10.2.2.4 Gate Driver Output Resistor
        5. 10.2.2.5 Gate to Source Resistor Selection
        6. 10.2.2.6 Estimating Gate Driver Power Loss
        7. 10.2.2.7 Estimating Junction Temperature
        8. 10.2.2.8 Selecting VCCI, VDDA/B Capacitor
          1. 10.2.2.8.1 Selecting a VCCI Capacitor
          2. 10.2.2.8.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 10.2.2.8.3 Select a VDDB Capacitor
        9. 10.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Component Placement Considerations
      2. 12.1.2 Grounding Considerations
      3. 12.1.3 High-Voltage Considerations
      4. 12.1.4 Thermal Considerations
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.10 Switching Characteristics

VVCCI = 3.3 V or 5.5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, load capacitance COUT = 0 pF, TJ = –40°C to +150°C unless otherwise noted(1).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tRISEOutput rise time, see Figure 8-4CVDD = 10 µF, COUT = 1.8 nF,
VVDDA, VVDDB = 12 V, f = 1 kHz		516ns
tFALLOutput fall time, see Figure 8-4CVDD = 10 µF, COUT = 1.8 nF ,
VVDDA, VVDDB = 12 V, f = 1 kHz		612ns
tPWminMinimum input pulse width that passes to output,
see Figure 8-1 and Figure 8-2		Output does not change the state if input signal less than tPWmin1020ns
tPDHLPropagation delay at falling edge, see Figure 8-3INx high threshold, VINH, to 10% of the output2840ns
tPDLHPropagation delay at rising edge, see Figure 8-3INx low threshold, VINL, to 90% of the output2840ns
tPWDPulse width distortion|tPDLHA – tPDHLA|, |tPDLHB– tPDHLB|
see Figure 8-3		5.5ns
tDMPropagation delays matching,
|tPDLHA – tPDLHB|, |tPDHLA – tPDHLB|, see Figure 8-3		f = 250kHz5ns
tVCCI+ to OUTVCCI Power-up Delay Time: UVLO Rise to OUTA, OUTB,
See Figure 8-7		INA or INB tied to VCCI4059µs
tVDD+ to OUTVDDA, VDDB Power-up Delay Time: UVLO Rise to OUTA, OUTB
See Figure 8-8		INA or INB tied to VCCI2335
|CMH|High-level common-mode transient immunity (See Section 8.7)Slew rate of GND vs. VSSA/B, INA and INB both are tied to VCCI; VCM=1000 V;100V/ns
|CML|Low-level common-mode transient immunity (See Section 8.7)Slew rate of GND vs. VSSA/B, INA and INB both are tied to GND; VCM=1000 V;100
(1) Parameters with only a typical value are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty.