SLUSDO2C June 2020 – February 2021 UCC21540-Q1
Figure 12-1 shows a 2-layer PCB layout example with the signals and key components labeled for the SOIC-14 DW package, which has Pin 12 and Pin 13 removed. For more detailed information, please refer to the UCC21540EVM design - "Using the UCC21540EVM - TI"
There are no PCB traces or copper between the primary and secondary side, which ensures isolation performance.
PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.
The location of the PCB cutout between the primary side and secondary sides, which ensures isolation performance.