SLUSDO2C June 2020 – February 2021 UCC21540-Q1
Channel 1 (Blue): Gate-source signal on the high side power transistor.
Channel 2 (Cyan): Gate-source signal on the low side power transistor.
Channel 3 (Pink): INA pin signal.
Channel 4 (Green): INB pin signal.
In Figure 10-5, INA and INB are sent complimentary 3.3-V, 20%/80% duty-cycle signals. The gate drive signals on the power transistor have a 200-ns dead time with 400V high voltage on the DC-Link, shown in the measurement section of Figure 10-5. Note that with high voltage present, lower bandwidth differential probes are required, which limits the achievable accuracy of the measurement.
Figure 10-6 shows a zoomed-in version of the waveform of Figure 10-5, with measurements for propagation delay and dead time. Importantly, the output waveform is measured between the power transistors’ gate and source pins, and is not measured directly from the driver OUTA and OUTB pins.