SLUSDO2C June 2020 – February 2021 UCC21540-Q1
The recommended input supply voltage (VCCI) for the UCC21540-Q1 is between 3 V and 5.5 V. The output bias supply voltage (VDDA/VDDB) ranges from 6.0 V to 18 V. The lower end of this bias supply range is governed by the internal under voltage lockout (UVLO) protection feature of each device. VDD and VCCI must not fall below their respective UVLO thresholds during normal operation. (For more information on UVLO see Section 9.3.1). The upper end of the VDDA/VDDB range depends on the maximum gate voltage of the power device being driven by the UCC21540-Q1. The recommended maximum VDDA/VDDB is 18 V.
A local bypass capacitor should be placed between the VDD and VSS pins, to supply current when the output goes high into a capacitive load. This capacitor should be positioned as close to the device as possible to minimize parasitic impedance. A low ESR, ceramic surface mount capacitor is recommended. If the bypass capacitor impedance is too large, resistive and inductive parasitics could cause the supply voltage seen at the IC pins to dip below the UVLO threshold unexpectedly. To filter high frequency noise between VDD and VSS, it can be helpful to place a second capacitor with lower impedance at higher frequency. As an example, the primary bypass capacitor could be 1 µF, with a secondary high frequency bypass capacitor of 100 nF.
Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of current drawn by the logic circuitry within the input side of the UCC21540-Q1, this bypass capacitor has a minimum recommended value of 100 nF.