SLUSDO2C June 2020 – February 2021 UCC21540-Q1
Whenever the supply voltage VCCI crosses from below the falling threshold VVCCI_OFF to above the rising threshold VVCCI_ON, and whenever the supply voltage VDDx crosses from below the falling threshold VVDDx_OFF to above the rising threshold VVDDx_ON, there is a delay before the outputs begin responding to the inputs. For VCCI UVLO this delay is defined as tVCCI+ to OUT, and is typically 40 µs. For VDDx UVLO this delay is defined as tVDD+ to OUT, and is typically 23 µs. TI recommends allowing some margin before driving input signals, to ensure the driver VCCI and VDD bias supplies are fully activated. Figure 8-7 and Figure 8-8 show the power-up UVLO delay timing diagram for VCCI and VDD.
Whenever the supply voltage VCCI crosses below the falling threshold VVCCI_OFF, or VDDx crosses below the falling threshold VVDDx_OFF, the outputs stop responding to the inputs and are held low within 1 µs. This asymmetric delay is designed to ensure safe operation during VCCI or VDDx brownouts.
When VCCI goes away but VDDx is present, outputs are held low; when VDDx is gone, outputs are CLAMPED low through the active pull down feature. For more detailed UVLO feature description, please check session Section 9.3.1.