SLUSDO2C June   2020  – February 2021 UCC21540-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     UCC21540-Q1 Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety-Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Minimum Pulses
    2. 8.2 Propagation Delay and Pulse Width Distortion
    3. 8.3 Rising and Falling Time
    4. 8.4 Input and Disable Response Time
    5. 8.5 Programmable Dead Time
    6. 8.6 Power-up UVLO Delay to OUTPUT
    7. 8.7 CMTI Testing
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 9.3.2 Input and Output Logic Table
      3. 9.3.3 Input Stage
      4. 9.3.4 Output Stage
      5. 9.3.5 Diode Structure in the UCC21540-Q1
    4. 9.4 Device Functional Modes
      1. 9.4.1 Disable Pin
      2. 9.4.2 Programmable Dead Time (DT) Pin
        1. 9.4.2.1 DT Pin Tied to VCCI
        2. 9.4.2.2 Connecting a Programming Resistor between DT and GND Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Designing INA/INB Input Filter
        2. 10.2.2.2 Select Dead Time Resistor and Capacitor
        3. 10.2.2.3 Select External Bootstrap Diode and its Series Resistor
        4. 10.2.2.4 Gate Driver Output Resistor
        5. 10.2.2.5 Gate to Source Resistor Selection
        6. 10.2.2.6 Estimating Gate Driver Power Loss
        7. 10.2.2.7 Estimating Junction Temperature
        8. 10.2.2.8 Selecting VCCI, VDDA/B Capacitor
          1. 10.2.2.8.1 Selecting a VCCI Capacitor
          2. 10.2.2.8.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 10.2.2.8.3 Select a VDDB Capacitor
        9. 10.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Component Placement Considerations
      2. 12.1.2 Grounding Considerations
      3. 12.1.3 High-Voltage Considerations
      4. 12.1.4 Thermal Considerations
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.9 Electrical Characteristics

VVCCI = 3.3 V or 5.0 V, 0.1-µF capacitor from VCCI to GND and 1-µF capacitor from VDDA/B to VSSA/B, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, DT pin tied to VCCI, CL = 0 pF, TJ = –40°C to +150°C unless otherwise noted(1)(2).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY CURRENTS
IVCCIVCCI quiescent currentVINA = 0 V, VINB = 0 V1.52.0mA
IVDDA, IVDDBVDDA and VDDB quiescent currentVINA = 0 V, VINB = 0 V1.01.8mA
IVCCIVCCI operating currentcurrent per channel (f = 500-kHz, 50% duty cycle)2.5mA
IVDDA, IVDDBVDDA and VDDB operating currentcurrent per channel (f = 500 kHz, 50% duty cycle), CL = 100 pF2.5mA
VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVCCI_ONUVLO Rising threshold2.552.72.85V
VVCCI_OFFUVLO Falling threshold2.352.52.65V
VVCCI_HYSUVLO Threshold hysteresis0.2V
UCC21540A-Q1 VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVDDA_ON, VVDDB_ON UVLO Rising threshold 5.0 5.5 5.9 V
VVDDA_OFF, VVDDB_OFF UVLO Falling threshold 4.7 5.2 5.6 V
VVDDA_HYS, VVDDB_HYS UVLO Threshold hysteresis 0.3 V
UCC21540-Q1 VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVDDA_ON, VVDDB_ON UVLO Rising threshold 8 8.5 9 V
VVDDA_OFF, VVDDB_OFF UVLO Falling threshold 7.5 8 8.5 V
VVDDA_HYS, VVDDB_HYS UVLO Threshold hysteresis 0.5 V
INA, INB AND DISABLE
VINAH, VINBH, VDISHInput high threshold voltage1.61.82V
VINAL, VINBL, VDISLInput low threshold voltage0.811.25V
VINA_HYS, VINB_HYS, VDIS_HYSInput threshold hysteresis0.8V
OUTPUT
IOA+, IOB+Peak output source currentCVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement24A
IOA-, IOB-Peak output sink current36A
ROHA, ROHBOutput resistance at high stateIOUT = –10 mA, ROHA, ROHB do not represent drive pull-up performance. See tRISE in and Section 9.3.4 for details.510Ω
ROLA, ROLBOutput resistance at low stateIOUT = 10 mA0.551.1Ω
VOHA, VOHBOutput voltage at high stateVVDDA, VVDDB = 12 V, IOUT = –10 mA11.911.95V
VOLA, VOLBOutput voltage at low stateVVDDA, VVDDB = 12 V, IOUT = 10 mA5.511mV
VOAPDA, VOAPDBDriver output (VOUTA, VOUTB) active pull downVVDDA and VVDDB unpowered, IOUTA, IOUTB = 200 mA 1.752.1V
DEAD TIME AND OVERLAP PROGRAMMING
Dead time, DTDT pin tied to VCCIOverlap determined by INA, INB-
RDT = 10 kΩ80100120ns
RDT = 20 kΩ160200240
RDT = 50 kΩ400500600
Dead time matching, |DTAB-DTBA|RDT = 10 kΩ-010ns
RDT = 20 kΩ-020
RDT = 50 kΩ-065
(1) Current direction in the testing conditions are defined to be positive into the pin and negative out of the specified terminal (unless otherwise noted)
(2) Parameters with only a typical value are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty.