SLUSD78C February   2019  – January 2023 UCC21750

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Safety-Related Certifications
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay
      1. 7.1.1 Regular Turn-OFF
    2. 7.2 Input Deglitch Filter
    3. 7.3 Active Miller Clamp
      1. 7.3.1 Internal On-chip Active Miller Clamp
    4. 7.4 Undervoltage Lockout (UVLO)
      1. 7.4.1 VCC UVLO
      2. 7.4.2 VDD UVLO
    5. 7.5 Desaturation (DESAT) Protection
      1. 7.5.1 DESAT Protection with Soft Turn-OFF
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power Supply
      2. 8.3.2  Driver Stage
      3. 8.3.3  VCC and VDD Undervoltage Lockout (UVLO)
      4. 8.3.4  Active Pulldown
      5. 8.3.5  Short Circuit Clamping
      6. 8.3.6  Internal Active Miller Clamp
      7. 8.3.7  Desaturation (DESAT) Protection
      8. 8.3.8  Soft Turn-Off
      9. 8.3.9  Fault (FLT, Reset, and Enable (RST/EN)
      10. 8.3.10 Isolated Analog to PWM Signal Function
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Filters for IN+, IN–, and RST/EN
        2. 9.2.2.2 PWM Interlock of IN+ and IN–
        3. 9.2.2.3 FLT, RDY, and RST/EN Pin Circuitry
        4. 9.2.2.4 RST/EN Pin Control
        5. 9.2.2.5 Turn-On and Turn-Off Gate Resistors
        6. 9.2.2.6 Overcurrent and Short Circuit Protection
        7. 9.2.2.7 Isolated Analog Signal Sensing
          1. 9.2.2.7.1 Isolated Temperature Sensing
          2. 9.2.2.7.2 Isolated DC Bus Voltage Sensing
        8. 9.2.2.8 Higher Output Current Using an External Current Buffer
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.2 PWM Interlock of IN+ and IN–

The UCC21750 features the PWM interlock for IN+ and IN– pins, which can be used to prevent the phase leg shoot through issue. As shown in Table 8-1, the output is logic low while both IN+ and IN– are logic high. When only IN+ is used, IN– can be tied to GND. To use the PWM interlock function, the PWM signal of the other switch in the phase leg can be sent to the IN– pin. As shown in Figure 9-2, the PWM_T is the PWM signal to top side switch, the PWM_B is the PWM signal to bottom side switch. For the top side gate driver, the PWM_T signal is given to the IN+ pin, while the PWM_B signal is given to the IN- pin; for the bottom side gate driver, the PWM_B signal is given to the IN+ pin, while PWM_T signal is given to the IN- pin. When both PWM_T and PWM_B signals are high, the outputs of both gate drivers are logic low to prevent the shoot through condition.

GUID-EFE3AB3B-C9E6-44F9-9E49-1B3459E4040A-low.gifFigure 9-2 PWM Interlock for a Half Bridge