SLUSDV7B October   2019  – March 2021 UCC23313-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Function
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Propagation Delay, rise time and fall time
    2. 7.2 IOH and IOL testing
    3. 7.3 CMTI Testing
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. Undervoltage Lockout (UVLO)
        2. Active Pulldown
        3. Short-Circuit Clamping
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Selecting the Input Resistor
        2. Gate Driver Output Resistor
        3. Estimate Gate-Driver Power Loss
        4. Estimating Junction Temperature
        5. Selecting VCC Capacitor
      3. 9.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 PCB Material
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWY|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power Supply Recommendations

The recommended input supply voltage (VCC) for the UCC23313-Q1 device is from to 33 V. The lower limit of the range of output bias-supply voltage (VCC) is determined by the internal UVLO protection feature of the device. VCC voltage should not fall below the UVLO threshold for normal operation, or else the gate-driver outputs can become clamped low for more than 20 μs by the UVLO protection feature. The higher limit of the VCC range depends on the maximum gate voltage of the power device that is driven by the UCC23313-Q1 device, and should not exceed the recommended maximum VCC of 33 V. A local bypass capacitor should be placed between the VCC and VEE pins, with a value of 220-nF to 10-μF for device biasing. TI recommends placing an additional 100-nF capacitor in parallel with the device biasing capacitor for high frequency filtering. Both capacitors should be positioned as close to the device as possible. Low-ESR, ceramic surface-mount capacitors are recommended.

If only a single, primary-side power supply is available in an application, isolated power can be generated for the secondary side with the help of a transformer driver such as Texas Instruments' SN6501 or SN6505A. For such applications, detailed power supply design and transformer selection recommendations are available in SN6501 Transformer Driver for Isolated Power Supplies data sheet and SN6505A Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet.