SLUSDV7B October   2019  – March 2021 UCC23313-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Function
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Propagation Delay, rise time and fall time
    2. 7.2 IOH and IOL testing
    3. 7.3 CMTI Testing
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. Undervoltage Lockout (UVLO)
        2. Active Pulldown
        3. Short-Circuit Clamping
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Selecting the Input Resistor
        2. Gate Driver Output Resistor
        3. Estimate Gate-Driver Power Loss
        4. Estimating Junction Temperature
        5. Selecting VCC Capacitor
      3. 9.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 PCB Material
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWY|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Estimate Gate-Driver Power Loss

The total loss, PG, in the gate-driver subsystem includes the power losses (PGD) of the UCC23313-Q1 device and the power losses in the peripheral circuitry, such as the external gate-drive resistor.

The PGD value is the key power loss which determines the thermal safety-related limits of the UCC23313-Q1 device, and it can be estimated by calculating losses from several components.

The first component is the static power loss, PGDQ, which includes power dissipated in the input stage (PGDQ_IN) as well as the quiescent power dissipated in the output stage (PGDQ_OUT) when operating with a certain switching frequency under no load. PGDQ_IN is determined by IF and VF and is given by Equation 5. The PGDQ_OUT parameter is measured on the bench with no load connected to VOUT pin at a given VCC, switching frequency, and ambient temperature. In this example, VCC is 15 V. The current on the power supply, with PWM switching at 10 kHz, is measured to be ICC = 1.33 mA . Therefore, use Equation 6 to calculate PGDQ_OUT.

Equation 5. GUID-176B0C88-37A3-4623-B132-D19AD96617C6-low.gif
Equation 6. GUID-2BD4868E-24A3-433D-B3D7-6607E4C6F8F7-low.gif

The total quiescent power (without any load capacitance) dissipated in the gate driver is given by the sum of Equation 5 and Equation 6 as shown in Equation 7

Equation 7. GUID-BDE4A6DB-A293-48D7-BB27-19CA280F5739-low.gif

The second component is the switching operation loss, PGDSW, with a given load capacitance which the driver charges and discharges the load during each switching cycle. Use Equation 8 to calculate the total dynamic loss from load switching, PGSW.

Equation 8. GUID-FDA5D234-4E99-4245-8649-386B740C3FD7-low.gif


  • QG is the gate charge of the power transistor at VCC.

So, for this example application the total dynamic loss from load switching is approximately 18 mW as calculated in Equation 9.

Equation 9. GUID-A5A7337E-54AB-4EC6-AE0B-BB7C5A4D2E02-low.gif

QG represents the total gate charge of the power transistor switching 520 V at 50 A, and is subject to change with different testing conditions. The UCC23313-Q1 gate-driver loss on the output stage, PGDO, is part of PGSW. PGDO is equal to PGSW if the external gate-driver resistance and power-transistor internal resistance are 0 Ω, and all the gate driver-loss will be dissipated inside the UCC23313-Q1. If an external turn-on and turn-off resistance exists, the total loss is distributed between the gate driver pull-up/down resistance, external gate resistance, and power-transistor internal resistance. Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4.5A/5.3A, however, it will be non-linear if the source/sink current is saturated. Therefore, PGDO is different in these two scenarios.

Case 1 - Linear Pull-Up/Down Resistor:

Equation 10. GUID-3B02450B-C482-41E6-87E8-43B831B3F830-low.gif

In this design example, all the predicted source and sink currents are less than 4.5 A and 5.3 A, therefore, use Equation 10 to estimate the UCC23313-Q1 gate-driver loss.

Equation 11. GUID-116ABC90-DC16-4B84-A192-3DD40F53B7D7-low.gif

Case 2 - Nonlinear Pull-Up/Down Resistor:

Equation 12. GUID-A54DC805-76D9-4362-A6E4-B6DDB6C04987-low.gif


  • VOUT(t) is the gate-driver OUT pin voltage during the turnon and turnoff period. In cases where the output is saturated for some time, this value can be simplified as a constant-current source (4.5 A at turnon and 5.3 A at turnoff) charging or discharging a load capacitor. Then, the VOUT(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted.

For some scenarios, if only one of the pullup or pulldown circuits is saturated and another one is not, the PGDO is a combination of case 1 and case 2, and the equations can be easily identified for the pullup and pulldown based on this discussion.

Use Equation 13 to calculate the total gate-driver loss dissipated in the UCC23313-Q1 gate driver, PGD.

Equation 13. GUID-E475B4EE-2A61-4A4F-B1D6-F451006F5633-low.gif