SLUSDV7B October 2019 – March 2021 UCC23313-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The total loss, P_{G}, in the gate-driver subsystem includes the power losses (P_{GD}) of the UCC23313-Q1 device and the power losses in the peripheral circuitry, such as the external gate-drive resistor.
The P_{GD} value is the key power loss which determines the thermal safety-related limits of the UCC23313-Q1 device, and it can be estimated by calculating losses from several components.
The first component is the static power loss, P_{GDQ}, which includes power dissipated in the input stage (P_{GDQ_IN}) as well as the quiescent power dissipated in the output stage (P_{GDQ_OUT}) when operating with a certain switching frequency under no load. P_{GDQ_IN} is determined by I_{F} and V_{F} and is given by Equation 5. The P_{GDQ_OUT} parameter is measured on the bench with no load connected to V_{OUT} pin at a given V_{CC}, switching frequency, and ambient temperature. In this example, V_{CC} is 15 V. The current on the power supply, with PWM switching at 10 kHz, is measured to be I_{CC} = 1.33 mA . Therefore, use Equation 6 to calculate P_{GDQ_OUT}.
The total quiescent power (without any load capacitance) dissipated in the gate driver is given by the sum of Equation 5 and Equation 6 as shown in Equation 7
The second component is the switching operation loss, P_{GDSW}, with a given load capacitance which the driver charges and discharges the load during each switching cycle. Use Equation 8 to calculate the total dynamic loss from load switching, P_{GSW}.
where
So, for this example application the total dynamic loss from load switching is approximately 18 mW as calculated in Equation 9.
Q_{G} represents the total gate charge of the power transistor switching 520 V at 50 A, and is subject to change with different testing conditions. The UCC23313-Q1 gate-driver loss on the output stage, P_{GDO}, is part of P_{GSW}. P_{GDO} is equal to P_{GSW} if the external gate-driver resistance and power-transistor internal resistance are 0 Ω, and all the gate driver-loss will be dissipated inside the UCC23313-Q1. If an external turn-on and turn-off resistance exists, the total loss is distributed between the gate driver pull-up/down resistance, external gate resistance, and power-transistor internal resistance. Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4.5A/5.3A, however, it will be non-linear if the source/sink current is saturated. Therefore, P_{GDO} is different in these two scenarios.
Case 1 - Linear Pull-Up/Down Resistor:
In this design example, all the predicted source and sink currents are less than 4.5 A and 5.3 A, therefore, use Equation 10 to estimate the UCC23313-Q1 gate-driver loss.
Case 2 - Nonlinear Pull-Up/Down Resistor:
where
For some scenarios, if only one of the pullup or pulldown circuits is saturated and another one is not, the P_{GDO} is a combination of case 1 and case 2, and the equations can be easily identified for the pullup and pulldown based on this discussion.
Use Equation 13 to calculate the total gate-driver loss dissipated in the UCC23313-Q1 gate driver, P_{GD}.