SLUSCM5A August 2017 – February 2018 UCC24612
UCC24612 uses the REG pin voltage to detect UVLO instead of the VDD pin voltage. When the REG voltage to the device has not yet reached the VREGON threshold, or has fallen below the UVLO threshold VREGOFF, the device operates in the low-power UVLO mode. In this mode, most internal functions are disabled and VDD current is IVDDstart, typically less than 120 µA. If the REG pin is above 2 V, there is an active pull-down from VG to VS to prevent SR turn-on due to noise. When the REG pin voltage is less than 2 V, there is a weak pull down from VG to VS and this also helps prevent false turn on of the SR MOSFET. The device exits UVLO mode when REG increases above the VREGON threshold.