SLUSD49A September   2017  – January 2019 UCC256303

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Hybrid Hysteretic Control
      2. 7.3.2  Regulated 12-V Supply
      3. 7.3.3  Feedback Chain
      4. 7.3.4  Optocoupler Feedback Signal Input and Bias
      5. 7.3.5  System External Shut Down
      6. 7.3.6  Pick Lower Block and Soft Start Multiplexer
      7. 7.3.7  Pick Higher Block and Burst Mode Multiplexer
      8. 7.3.8  VCR Comparators
      9. 7.3.9  Resonant Capacitor Voltage Sensing
      10. 7.3.10 Resonant Current Sensing
      11. 7.3.11 Bulk Voltage Sensing
      12. 7.3.12 Output Voltage Sensing
      13. 7.3.13 High Voltage Gate Driver
      14. 7.3.14 Protections
        1. 7.3.14.1 ZCS Region Prevention
        2. 7.3.14.2 Over Current Protection (OCP)
        3. 7.3.14.3 Over Output Voltage Protection (VOUTOVP)
        4. 7.3.14.4 Over Input Voltage Protection (VINOVP)
        5. 7.3.14.5 Under Input Voltage Protection (VINUVP)
        6. 7.3.14.6 Boot UVLO
        7. 7.3.14.7 RVCC UVLO
        8. 7.3.14.8 Over Temperature Protection (OTP)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Burst Mode Control
      2. 7.4.2 Soft-Start and Burst-Mode Threshold
      3. 7.4.3 System States and Faults State Machine
      4. 7.4.4 Waveform Generator State Machine
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 Design Considerations for Adaptive Dead-Time
        13. 8.2.2.13 LLC Rectifier Diodes
        14. 8.2.2.14 LLC Output Capacitors
        15. 8.2.2.15 BLK Pin Voltage Divider
        16. 8.2.2.16 BW Pin Voltage Divider
        17. 8.2.2.17 ISNS Pin Differentiator
        18. 8.2.2.18 VCR Pin Capacitor Divider
        19. 8.2.2.19 Burst Mode Programming
        20. 8.2.2.20 Soft-Start Capacitor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 VCC Pin Capacitor
    2. 9.2 Boot Capacitor
    3. 9.3 RVCC Pin Capacitor
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support (if applicable)
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDB|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Burst Mode Control

The efficiency of an LLC converter power stage drops rapidly with falling output power. To maintain reasonable light load efficiency it is necessary to operate the LLC converter in burst mode. In this mode the LLC converter operates at relatively high power for a short burst period and then all switching is stopped for a space period. During the Burst period excess charge is transferred to and stored in the output capacitor. During the Space period this stored charge is used to supply the load current. Providing an effective light-load scheme is a particular problem for an LLC controller that is located on the primary side of the isolation barrier. This is because the feedback demand signal (VCOMP) is mainly a function of input/output voltage ratio and only loosely related to load current. The normal method of placing a couple of thresholds in the VCOMP voltage window to switch OFF and ON the LLC converter does not work effectively. Another issue with the conventional method is that when burst on, the switching pulses are determined by VCOMP, which is usually at initial burst on, and decays as the output voltage rises. The resulting inductor current will be big at first and then decays. This is not optimal because the big current at first may create mechanical vibration. The high switching frequency afterwards may cause two much switching loss.

For an advanced burst mode, the following features are desired:

  • The power delivered by each burst should be relatively constant for a certain load.
  • The Burst power is set high enough to provide reasonable LLC converter efficiency and low enough to avoid acoustic noise and excessive output voltage ripple.
  • When burst on, the average capacitor voltage should settle to VIN/2 as fast as possible for best efficiency.
  • The switching frequency or burst power level of each burst pulse should be optimized for efficient operation.
  • The burst pattern of each burst should be relatively constant.
  • There should be no audible noise.
  • Burst mode performance should be consistent across input voltage range.

The HHC method makes the control of the burst mode very straight forward. The block diagram is a functionally accurate description of the burst mode control method in UCC256303.

UCC256303 fig32_sluscu6.gifFigure 36. Burst Mode Control Block Diagram

The control effort is selected between the higher of the two signals: 1) the voltage loop compensator output (VCOMP) or 2) the Burst Mode Threshold level (BMT). When VCOMP goes below BMT, continue switching for a fixed number of switching cycles, then stop. Always switch while COMP is higher than BMT. If soft start isn’t done yet, send the COMP (controlled by soft start ramp). BMT is programmable and adaptively changed with input voltage. The last pulse of each burst on period is turned off when the resonant capacitor voltage equals VIN/2. In HHC method, this is approximately equivalent to VCR node voltage equals the common mode voltage VCM. This operation keeps the resonant capacitor voltage to about VIN/2 for each burst off period, thus enabling the burst pattern to settle as soon as possible during burst on period.