SLUSD90E June   2019  – February 2021 UCC256402 , UCC256403 , UCC256404

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
    1.     Device Comparison Table
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hybrid Hysteretic Control
      2. 7.3.2 Regulated 13-V Supply
      3. 7.3.3 Feedback Chain
        1. 7.3.3.1 Optocoupler Feedback Signal Input and Bias
        2. 7.3.3.2 FB Pin Voltage Clamp
        3. 7.3.3.3 "Pick Lower Value" Block and Soft Start Multiplexer
        4. 7.3.3.4 Pick Higher Block and Burst Mode Multiplexer
        5. 7.3.3.5 VCR Comparators
      4. 7.3.4 Resonant Capacitor Voltage Sensing
      5. 7.3.5 Resonant Current Sensing
      6. 7.3.6 Bulk Voltage Sensing
      7. 7.3.7 Output Voltage Sensing
      8. 7.3.8 High Voltage Gate Driver
        1. 7.3.8.1 Adaptive Dead Time Control
      9. 7.3.9 Protections
        1. 7.3.9.1 ZCS Region Prevention
        2. 7.3.9.2 Over Current Protection (OCP)
        3. 7.3.9.3 Bias Winding Over Voltage Protection (BWOVP)
        4. 7.3.9.4 Input Under Voltage Protection (VINUVP)
        5. 7.3.9.5 Input Over Voltage Protection (VINOVP)
        6. 7.3.9.6 Boot UVLO
        7. 7.3.9.7 RVCC UVLO
        8. 7.3.9.8 Over Temperature Protection (OTP)
    4. 7.4 Device Functional Modes
      1. 7.4.1 High Voltage Start-Up
      2. 7.4.2 X-Capacitor Discharge
      3. 7.4.3 Burst Mode Control
        1. 7.4.3.1 Soft-Start and Burst-Mode Threshold
        2. 7.4.3.2 BMTL/BMTH Ratio Programming
      4. 7.4.4 System State Machine
  8. 8 Power Supply Recommendations
    1. 8.1 VCC Pin Capacitor
    2. 8.2 Boot Capacitor
    3. 8.3 RVCC Pin Capacitor
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Related Links
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.3.1 Soft-Start and Burst-Mode Threshold

The soft-start programming and burst mode threshold programming are multiplexed on the pin LL/SS. In addition, when ZCS region operation happens, this pin is pulled down to ground through a diode to increase the switching frequency. The pin block diagram is shown in Figure 7-19.

Figure 7-20 shows the timing diagram of the LL/SS pin programming. It includes 5 phases:

  • SS pull low phase - LL/SS pin is internally pulled low with a typical 1.2 kΩ resistor to ground.
  • SS initial voltage program phase - The internal pull low is released. As shown in Figure 7-19, LL/SS pin is typically connected with a resistor divider from RVCC and a capacitor to ground. When the internal pull low circuit is released, LL/SS pin voltage can be charged up depending on the external resistor and capacitor. This phase ends when charge boot stage is completed and it has a fixed time of tSSInitVolPrgm.
  • Soft start phase - An internal constant current source charges the soft start capacitor right after the charge boot stage, and ends when FBreplica becomes lower than the LL/SS pin voltage. During this phase, LL/SS pin voltage is used as the control effort Vcomp. The slow ramp up of LL/SS pin helps the LLC operate at a higher switching frequency when the output voltage is not established yet during startup. This can avoid the large inrush current during startup.
  • BMTL settling phase - When soft start phase is completed, LL/SS pin is used for burst mode threshold programming. As described in Section 7.4.3, two burst mode thresholds are used. During this phase, BMTH is fixed at either 0.6V (1.2 V if BW option 7 is selected). BMTL is also fixed which is determined by the programmed ratio of BMTL/BMTH. The typical duration of this phase is 600 us.
  • BMTL and BMTH programming/setting phase - LL/SS pin is buffered at 3.5 V during this phase. Depending on the resistors connected to the pin, LL/SS pin could either sink or source current. If LL/SS pin sinks current, the current will be internally mirrored to flow through RLL, and the voltage on RFB is the programmed voltage of BMTH. If LL/SS pin sources current, the programmed voltage of BMTH is set to minimal. If the programmed voltage of BMTH is different from the initial voltage, BMTH ramps to the target value at a refresh frequency of every 200 us. The slow refresh frequency makes sure that BMTH does not change due to the noise on LL/SS pin. BMTL follows the change of BMTH based on the programmed ratio of BMTL/BMTH.

The programmability of the SS initial voltage provides a freedom to limit the maximum switching frequency during startup. This helps to prevent hard switching due to excessively high switching frequency. For applications that require very high switching frequency during startup, an option is also provided to disable the SS initial voltage programming through BW pin, as described in Section 7.4.3.2. If this option is selected, LL/SS pin continues pull low with the internal 1.2 kΩ resistor during the SS initial voltage program phase.

GUID-F67F7028-B40B-424D-95E8-C82FB0B4AA26-low.gifFigure 7-19 LL/SS Block Diagram
GUID-26E423E3-A837-4B14-97F2-99D3ED43FFEA-low.gifFigure 7-20 Timing Diagram of LL/SS Pin Programming