SLUSD90E June   2019  – February 2021 UCC256402 , UCC256403 , UCC256404


  1. Features
  2. Applications
  3. Description
  4. Revision History
    1.     Device Comparison Table
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hybrid Hysteretic Control
      2. 7.3.2 Regulated 13-V Supply
      3. 7.3.3 Feedback Chain
        1. Optocoupler Feedback Signal Input and Bias
        2. FB Pin Voltage Clamp
        3. "Pick Lower Value" Block and Soft Start Multiplexer
        4. Pick Higher Block and Burst Mode Multiplexer
        5. VCR Comparators
      4. 7.3.4 Resonant Capacitor Voltage Sensing
      5. 7.3.5 Resonant Current Sensing
      6. 7.3.6 Bulk Voltage Sensing
      7. 7.3.7 Output Voltage Sensing
      8. 7.3.8 High Voltage Gate Driver
        1. Adaptive Dead Time Control
      9. 7.3.9 Protections
        1. ZCS Region Prevention
        2. Over Current Protection (OCP)
        3. Bias Winding Over Voltage Protection (BWOVP)
        4. Input Under Voltage Protection (VINUVP)
        5. Input Over Voltage Protection (VINOVP)
        6. Boot UVLO
        7. RVCC UVLO
        8. Over Temperature Protection (OTP)
    4. 7.4 Device Functional Modes
      1. 7.4.1 High Voltage Start-Up
      2. 7.4.2 X-Capacitor Discharge
      3. 7.4.3 Burst Mode Control
        1. Soft-Start and Burst-Mode Threshold
        2. BMTL/BMTH Ratio Programming
      4. 7.4.4 System State Machine
  8. Power Supply Recommendations
    1. 8.1 VCC Pin Capacitor
    2. 8.2 Boot Capacitor
    3. 8.3 RVCC Pin Capacitor
  9. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Related Links
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Resonant Capacitor Voltage Sensing

The resonant capacitor voltage sense pin senses the resonant capacitor voltage through a capacitor divider. Inside the device, two well matched, controlled current sources are connected to the VCR pin to generate the frequency compensation ramp. The on/off control signals of the two current sources come from the waveform generator block.

During waveform generator IDLE state or before startup, the VCR node is clamped to VCM. This action will help reduce the startup peak current, and help the VCR voltage to settle down quickly during burst mode.

GUID-86FC388C-BE0A-425C-810D-A4AD7A68C9CD-low.gifFigure 7-5 VCR Block Diagram

The ramp current on/off sequence is shown in Figure 7-6. The ramp current is on all the time. It changes direction at the falling edge of the high-side on or low-side on signal.

GUID-83E9F722-7E06-4F53-9CFC-6AD6D60037C2-low.gifFigure 7-6 VCR Compensation Ramp Current On/Off

On the VCR pin, a capacitor divider is used to combine the resonant capacitor waveform and the compensation ramp waveform. Adjusting the size of the external capacitors can change the contribution of charge control and direct frequency control. Assuming the divided down version of the resonant capacitor voltage by the capacitor divider is Vdiv, the compensation ramp current resultant voltage on the VCR pin is Vramp. If Vdiv is much larger than Vramp, the control method is similar to charge control, in which the control effort is proportional to the input charge of one switching cycle. If Vramp is much larger than Vdiv, the control method is similar to direct frequency control, in which the control effort is proportional to the switching frequency. The most optimal transient response can be achieved by adjusting the ratio between Vdiv and Vramp.