During burst off period, power consumed by the high-side gate driver from the HB pin must be drawn from CBOOT and will cause its voltage to decay. At the start of the next burst period there must be sufficient voltage remaining on CBOOT to power the high-side gate driver until the conduction period of LO allows it to be replenished from CRVCC. The power consumed by the high-side driver during this burst off period will therefore have a direct impact on the size and cost of capacitors that must be connected to HB and RVCC.
Assume the system has a maximum burst off period of 150 ms and the bootstrap diode has a forward voltage drop of 1V. Target a minimum bootstrap voltage of 8 V to avoid UVLO fault. The maximum allowable voltage drop on the boot capacitor is:
Boot capacitor can then be sized: