SLUSD90E June   2019  – February 2021 UCC256402 , UCC256403 , UCC256404

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
    1.     Device Comparison Table
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hybrid Hysteretic Control
      2. 7.3.2 Regulated 13-V Supply
      3. 7.3.3 Feedback Chain
        1. 7.3.3.1 Optocoupler Feedback Signal Input and Bias
        2. 7.3.3.2 FB Pin Voltage Clamp
        3. 7.3.3.3 "Pick Lower Value" Block and Soft Start Multiplexer
        4. 7.3.3.4 Pick Higher Block and Burst Mode Multiplexer
        5. 7.3.3.5 VCR Comparators
      4. 7.3.4 Resonant Capacitor Voltage Sensing
      5. 7.3.5 Resonant Current Sensing
      6. 7.3.6 Bulk Voltage Sensing
      7. 7.3.7 Output Voltage Sensing
      8. 7.3.8 High Voltage Gate Driver
        1. 7.3.8.1 Adaptive Dead Time Control
      9. 7.3.9 Protections
        1. 7.3.9.1 ZCS Region Prevention
        2. 7.3.9.2 Over Current Protection (OCP)
        3. 7.3.9.3 Bias Winding Over Voltage Protection (BWOVP)
        4. 7.3.9.4 Input Under Voltage Protection (VINUVP)
        5. 7.3.9.5 Input Over Voltage Protection (VINOVP)
        6. 7.3.9.6 Boot UVLO
        7. 7.3.9.7 RVCC UVLO
        8. 7.3.9.8 Over Temperature Protection (OTP)
    4. 7.4 Device Functional Modes
      1. 7.4.1 High Voltage Start-Up
      2. 7.4.2 X-Capacitor Discharge
      3. 7.4.3 Burst Mode Control
        1. 7.4.3.1 Soft-Start and Burst-Mode Threshold
        2. 7.4.3.2 BMTL/BMTH Ratio Programming
      4. 7.4.4 System State Machine
  8. 8 Power Supply Recommendations
    1. 8.1 VCC Pin Capacitor
    2. 8.2 Boot Capacitor
    3. 8.3 RVCC Pin Capacitor
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Related Links
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

All voltages are with respect to GND, -40°C < TJ = TA < 125°C, VCC = 15 V, currents are positive into and negative out of the specified terminal, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
VCCShort Below this threshold, use reduced start up current For UCC256402, UCC256402A, UCC256404, UCC256404A, UCC256404B 0.3 0.5 0.8 V
VCCReStartJfet Below this threshold, re-enable JFET. For UCC256402, UCC256402A, UCC256404, UCC256404A, UCC256404B 9.35 9.65 9.95 V
VCCStartSelf Startup when VCC is above this level For UCC256402, UCC256402A, UCC256404, UCC256404A, UCC256404B 25 26 28 V
VCCStartSwitching Startup when VCC is above this level For UCC256403, UCC256403A 10.9 V
VCCUVLOrising VCC under voltage lockout voltage (rising) 7.85 8.25 8.70 V
VCCUVLOHYS VCC under voltage lockout voltage hysteresis 0.15 0.25 0.35 V
SUPPLY CURRENT
ICCSleep Current drawn from VCC rail during burst off period 650 780 950 µA
ICCRun Current drawn from VCC Pin while gate is switching. Excluding Gate Current Dead time = 1 µs maximum dead time 1.8 2.2 2.7 mA
REGULATED SUPPLY
VRVCC Regulated supply voltage VCC = 15 V, no load 12.7 13 13.45 V
Regulated supply voltage VCC = 15 V, 100 mA load 12.4 13 13.45 V
Regulated supply voltage VCC = 13 V, no load 12.7 12.98 V
Regulated supply voltage VCC = 13 V, 30 mA load 12.4 12.6 V
VRVCCUVLO RVCC under voltage lock out voltage 6.5 7 7.5 V
HIGH VOLTAGE STARTUP
IHVLow Reduced startup pin current VHV = 20 V, VCC = 0 V 0.3 0.5 0.65 mA
IHVHigh Full startup pin current VHV = 20 V, VCC = 4 V 7.6 10.20 13.5 mA
IHVLeak HV current source leakage current VHV = 600 V 1 4 µA
IHVZCD Highest AC zero crossing detection test current For UCC256404B 1.0 1.3 1.6 mA
For UCC256404, UCC256404A 1.4 1.7 2.1 mA
IHVZCDStep AC zero crossing detection test current steps 0.38 mA
IXCAPDischarge X-cap discharge current 8.9 11.5 13.5 mA
Vzero-crossing HV pin voltage threshold that zero-crossing is detected 8 9 11 V
tXCAPZCD AC zero crossing detection window length for first three test current stage (1) 10 12 14 ms
tXCAPZCDLast AC zero crossing detection window length for final test current stage (1) 43 46 52 ms
tXCAPIdle AC zero crossing detection idle period length (1) 635 700 772 ms
tXCAPDischarge Time for X-cap discharge current active (1) 327 360 390 ms
tXCAPJFETON Time of first X-cap detection after JFETON (1) 12 ms
BULK VOLTAGE SENSE
VBLKStart BLK voltage that allows LLC to start switching For UCC256402, UCC256402A, UCC256403, UCC256403A 2.94 3 3.06 V
For UCC256404, UCC256404A, UCC256404B 0.98 1 1.02 V
VBLKStop BLK voltage that forces LLC operation to stop For UCC256402, UCC256402A, UCC256403, UCC256403A 2.15 2.2 2.25 V
For UCC256404, UCC256404A, UCC256404B 0.88 0.9 0.925 V
VBLKOVPRise BLK over voltage protection rising threshold For UCC256402A 3.92 4.0 4.08 V
VBLKOVPFall BLK over voltage protection falling threshold For UCC256402A 3.72 3.8 3.88 V
FEEDBACK PIN
RFBInternal Internal pull down resistor value 90 100 110 kΩ
IFB FB internal current source For UCC256402, UCC256402A, UCC256404, UCC256404A, UCC256404B 73 82 91 µA
For UCC256403, UCC256403A 147 164 182 µA
VFB FB pin voltage when FB pin sink current is at (IFB - 50 µA) 5.6 V
ΔVFB FB pin voltage variation when FB pin sink current ranges from (IFB - 50 µA) to (IFB - 5 µA) 0.28 V
ΔVclamp FB pin voltage variation when FB pin sink current ranges from (IFB - 5 µA) to (IFB + 5 µA) 0.4 V
IFBclamp Maximum FB internal current source when FB is clamped 82 μA
ΔVFBclamp FB pin voltage variation when FB pin sink current ranges from (IFB + 5 µA) to (IFB + IFBClamp - 5 µA) 0.25 V
f-3dB Feedback chain -3dB cut off frequency (2) 1 MHz
RESONANT CURRENT SENSE
VISNS_OCP1 OCP1 threshold 3.9 4 4.1 V
VISNS_OCP1_SS OCP1 threshold during soft start 4.85 5 5.15 V
VISNS_OCP2 OCP2 threshold 0.57 0.6 0.63 V
VISNS_OCP3 OCP3 threshold 0.40 0.43 0.46 V
tISNS_OCP2 The time the average input current needs to stay above OCP2 threshold before OCP2 is triggered (1) 2 ms
tISNS_OCP3 The time the average input current needs to stay above OCP3 threshold before OCP3 is triggered (1) 50 ms
VIpolarityHyst Resonant current polarity detection hysteresis 16 30 44 mV
nOCP1 Number of OCP1 cycles before OCP1 fault is tripped (1) 4
RESONANT CAPACITOR VOLTAGE SENSE
VCM Internal common mode voltage 2.90 3 3.14 V
IRAMP Frequency compensation ramp current source value 1.84 2 2.16 mA
IMismatch Pull up and pull down ramp current source mismatch (3) -1.25 1.25 %
GATE DRIVER
VLOL LO output low voltage Isink = 20 mA 0.02 0.05 0.12 V
VRVCC - VLOH LO output high voltage Isource = 20 mA 0.10 0.18 0.3 V
VHOL - VHS HO output low voltage Isink = 20 mA 0.02 0.05 0.12 V
VHB - VHOH HO output high voltage Isource = 20 mA 0.10 0.18 0.3 V
VHB-HSUVLOFall High side gate driver UVLO falling threshold 6.6 7.25 7.75 V
VHB-HSUVLOHys High side gate driver UVLO threshold hysteresis 0.78 0.9 1.05 V
Isource_pk_HO HO peak source current (2) -0.6 A
Isource_pk_LO LO peak source current (2) -0.6 A
Isink_pk_HO HO peak sink current (2) 1.2 A
Isink_pk_LO LO peak sink current (2) 1.2 A
BOOTSTRAP
IBOOT_QUIESCENT (HB - HS) quiescent current HB - HS = 12 V 42 62 80 µA
IBOOT_LEAK HB to GND leakage current VHB = 600 V 0.40 5.40 µA
tChargeBoot Length of charge boot state 230 265 300 µs
SOFT START AND BURST MODE
ISSUp Current output from SS pin to charge up the soft start capacitor 26 36 45 µA
RSSDown SS pin pull down resistance ZCS or OCP1 300 370 450 Ω
tSSInitVolPrgm SS initial voltage programming time (1) 720 776 830 µs
RLL LL/SS voltage scaling resistor value 92 98 106 kΩ
Nburst Minimum number of pulses in each burst packet (including burst soft on/off pulses) For UCC256402, UCC256402A, UCC256403A,  UCC256404A 16
For UCC256403, UCC256404, UCC256404B 40
Nsoftmax Maximum number of pulses for burst soft on/off 7
Ksoft Minimal ratio of Vcomp/VFBreplica during burst soft on/off 0.33
VLLVolPrgm LL pin voltage during the burst mode exit threshold (BMTH) programming 3.5 V
BMTHmin Minimal burst mode exit threshold 0.2 V
BMTLmin Minimal burst mode entry threshold 0.2 V
BIAS WINDING
VBWOVPos Output voltage OVP - Positive Threshold 3.86 4 4.12 V
VBWOVNeg Output voltage OVP - Negative Threshold -4.12 -4 -3.86 V
nBWOV Number of BW OVP cycles before BW OVP fault is tripped (1) 5
IBWPrgm BW pin sourcing current for BMTL/BMTH programming 51 54 57 µA
tBWPrgm BMTL/BMTH programming time 2 ms
KBMTL/BMTH1 Ratio of BMTL/BMTH Option 1 0.95
KBMTL/BMTH2 Ratio of BMTL/BMTH Option 2 1
KBMTL/BMTH3 Ratio of BMTL/BMTH Option 3 0.9
KBMTL/BMTH4 Ratio of BMTL/BMTH Option 4 0.8
KBMTL/BMTH5 Ratio of BMTL/BMTH Option 5 0.6
KBMTL/BMTH6 Ratio of BMTL/BMTH Option 6 0.6
KBMTL/BMTH7 Ratio of BMTL/BMTH Option 7 (Burst mode disable) 0.4
RBWPrgm1 BW pin equivalent resistance to choose BMTL/BMTH ratio option 1 (2) 24730 Ω
RBWPrgm2 BW pin equivalent resistance to choose BMTL/BMTH ratio option 2 (2) 17125 19976 Ω
RBWPrgm3 BW pin equivalent resistance to choose BMTL/BMTH ratio option 3 (2) 12562 13624 Ω
RBWPrgm4 BW pin equivalent resistance to choose BMTL/BMTH ratio option 4 (2) 9018 9813 Ω
RBWPrgm5 BW pin equivalent resistance to choose BMTL/BMTH ratio option 5 (2) 6478 6849 Ω
RBWPrgm6 BW pin equivalent resistance to choose BMTL/BMTH ratio option 6(2) 4450 4732 Ω
RBWPrgm7 BW pin equivalent resistance to choose BMTL/BMTH ratio option 7 (Burst mode disable) (2) 2422 3038 Ω
ADAPTIVE DEADTIME
dVHS/dt Detectable slew rate (1) -0.1 -50 V/ns
FAULT RECOVERY
tPauseTimeOut Paused timer (1) 1 s
THERMAL SHUTDOWN
TJ_r Thermal shutdown temperature (1) Temperature rising 125 145 °C
TJ_H Thermal shutdown hsyterisis (1) 10 °C
(1) Not tested in production. Ensured by characterization
(2) Not tested in production. Ensured by design
(3) IMismatch calculated as [IPU-(IPD+IPU)/2]/[(IPD+IPU)/2]