SLUS822C June   2008  – August 2016 UCC27200-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Stages
        1. 7.3.1.1 Undervoltage Lockout (UVLO)
        2. 7.3.1.2 Level Shift
        3. 7.3.1.3 Boot Diode
        4. 7.3.1.4 Output Stages
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Switching the MOSFETs
      2. 8.1.2 Dynamic Switching of the MOSFETs
      3. 8.1.3 Delay Matching and Narrow Pulse Widths
      4. 8.1.4 Boot-Diode Performance
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Threshold Type
        2. 8.2.2.2 VDD Bias Supply Voltage
        3. 8.2.2.3 Peak Source and Sink Currents
        4. 8.2.2.4 Propagation Delay
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resource
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The UCC27200-Q1 and UCC27201-Q1 devices are high-side and low-side drivers. The high-side and low-side each have independent inputs, which allow maximum flexibility of input control signals in the application. The boot diode for the high-side driver bias supply is internal to the UCC27200-Q1 and UCC27201-Q1. The UCC27200-Q1 is the CMOS-compatible input version and the UCC27201-Q1 is the TTL-version or logic-compatible version. The high-side driver is referenced to the switch node (HS), which is typically the source pin of the high-side MOSFET and drain pin of the low-side MOSFET. The low-side driver is referenced to VSS, which is typically ground. The functions contained are the input stages, UVLO protection, level shift, boot diode, and output driver stages.

NOTE

The term UCC2720x-Q1 applies to both the UCC27200-Q1 and UCC27201-Q1.

7.2 Functional Block Diagram

UCC27200-Q1 UCC27201-Q1 fig21_lus746.gif

7.3 Feature Description

7.3.1 Input Stages

The input stages provide the interface to the PWM output signals. The input impedance of the UCC27200-Q1 is 200 kΩ nominal and input capacitance is approximately 2 pF. The 200 kΩ is a pulldown resistance to VSS (ground). The CMOS-compatible input of the UCC27200-Q1 provides a rising threshold of 48% of VDD and falling threshold of 45% of VDD. The inputs of the UCC27200-Q1 are intended to be driven from 0 to VDD levels.

The input stages of the UCC27201-Q1 incorporate an open-drain configuration to provide the lower input thresholds. The input impedance is 200 kΩ nominal and input capacitance is approximately 4 pF. The 200 kΩ is a pulldown resistance to VSS (ground). The logic level-compatible input provides a rising threshold of 1.7 V and a falling threshold of 1.6 V.

7.3.1.1 Undervoltage Lockout (UVLO)

The bias supplies for the high-side and low-side drivers have UVLO protection. VDD as well as VHB to VHS differential voltages are monitored. The VDD UVLO disables both drivers when VDD is below the specified threshold. The rising VDD threshold is 7.1 V with 0.5-V hysteresis. The VHB UVLO disables only the high-side driver when the VHB to VHS differential voltage is below the specified threshold. The VHB UVLO rising threshold is 6.7 V with 0.4-V hysteresis.

7.3.1.2 Level Shift

The level-shift circuit is the interface from the high-side input to the high-side driver stage, which is referenced to the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides excellent delay matching with the low-side driver.

7.3.1.3 Boot Diode

The boot diode necessary to generate the high-side bias is included in the UCC2720x-Q1 family of drivers. The diode anode connects to VDD and the cathode connects to VHB. With the VHB capacitor connected to HB and the HS pins, the VHB capacitor charge refreshes every switching cycle when HS transitions to ground. The boot diode provides fast recovery times, low diode resistance, and a voltage rating margin that allow for efficient and reliable operation.

7.3.1.4 Output Stages

The output stages are the interface to the power MOSFETs in the power train. High-slew rate, low resistance, and high-peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The low-side output stage reference is from VDD to VSS and the high-side output stage reference is from VHB to VHS.

7.4 Device Functional Modes

The device operates in normal mode and UVLO mode. See Undervoltage Lockout (UVLO) for information on UVLO operation mode. In the normal mode, the output state is dependent on states of the HI and LI pins. Table 1 lists the output states for different input pin combinations.

Table 1. Device Logic Table

HI PIN LI PIN HO(1) LO(2)
L L L L
L H L H
H L H L
H H H H
(1) HO is measured with respect to HS.
(2) LO is measured with respect to VSS.