SLUSC72B May   2015  – March 2016 UCC27201A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Stages
        1. 7.3.1.1 UVLO (Under Voltage Lockout)
        2. 7.3.1.2 Level Shift
        3. 7.3.1.3 Boot Diode
        4. 7.3.1.4 Output Stages
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching the MOSFETs
        2. 8.2.2.2 Dynamic Switching of the MOSFETs
        3. 8.2.2.3 Delay Matching and Narrow Pulse Widths
        4. 8.2.2.4 Boot Diode Performance
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DDA Power Pad
8-Pin SOIC-8
(Top View)
UCC27201A-Q1 pinout_slusC72.gif
Pin VSS and the exposed thermal die pad are internally connected.
DMK Package
10-Pin VSON
Top View
UCC27201A-Q1 dmk_slusc72.gif
Pin VSS and the exposed thermal die pad are internally connected.

Pin Functions

PIN I/O(2) DESCRIPTION
NAME DDA DMK
HB 2 2 P High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass capacitor is 0.022 μF to 0.1 μF, the value is dependant on the gate charge of the high-side MOSFET however.
HI 5 7 I High-side input.
HO 3 3 O High-side output. Connect to the gate of the high-side power MOSFET.
HS 4 4 P High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin.
LI 6 8 I Low-side input.
LO 8 10 O Low-side output. Connect to the gate of the low-side power MOSFET.
N/C – 5/6 - No connection. Pins labeled N/C have no connection.
PowerPAD™ Pad(1) Pad(1) G Connect to a large thermal mass trace or GND plane to dramatically improve thermal performance.
VDD 1 1 P Positive supply to the lower gate driver. De-couple this pin to VSS (GND). Typical decoupling capacitor range is 0.22 μF to 1.0 μF.
VSS 7 9 G Negative supply terminal for the device which is generally grounded.
(1) Pin VSS and the exposed thermal die pad are internally connected on the DDA and DMK packages. Electrically referenced to VSS (GND).
(2) P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output