9.2.2.1 Input-to-Output Logic

The design should specify which type of input-to-output configuration should be used. The UCC27523 device can provide dual inverting input to output with enable control. The UCC27524 device can provide dual non-inverting input to output with enable control. The UCC27525 device can provide one inverting and one non-inverting input to output control. If turning on the power MOSFET or IGBT when the input signal is in high state is preferred, then the non-inverting configuration must be selected. If turning off the power MOSFET or IGBT when the input signal is in high state is preferred, the inverting configuration must be chosen. UCC27526 has dual configuration channel. Each Channel of UCC27526 device can be configured in either an inverting or non-inverting input-to-output configuration using the INx– or INx+ pins respectively like in Figure 35 and Figure 36. To configure the channel for use in inverting mode, tie the INx+ pin to VDD and apply the input signal to the INx– pin. For the non-inverting configuration, tie the INx– pin to GND and apply the input signal to the INx+ pin.

9.2.2.2 Enable and Disable Function

Certain applications demand independent control of the output state of the driver. The UCC27523/4/5 device offers two independent enable pins ENx for exclusive control of each driver channels as listed in Table 2.

The UCC27526 device does not feature dedicated enable pins. However, as mentioned earlier, an enable/disable function can be easily implemented in UCC27526 using the unused input pin. When INx+ is pulled-down to GND or INx– is pulled-down to VDD, the output is disabled as listed in Table 3. Thus INx+ pin can be used like an enable pin that is based on active high logic, while INx– can be used like an enable pin that is based on active low logic. It is important to note that while the ENA, ENB pins in the UCC27523/4/5 are allowed to be in floating condition during standard operation and the outputs will be enabled, the INx+, INx– pins in UCC27526 are not allowed to be floating because this will disable the outputs.

9.2.2.3 VDD Bias Supply Voltage

The bias supply voltage to be applied to the VDD pin of the device should never exceed the values listed in the Recommended Operating Conditions. However, different power switches demand different voltage levels to be applied at the gate terminals for effective turnon and turnoff. With certain power switches, a positive gate voltage may be required for turnon and a negative gate voltage may be required for turnoff, in which case the VDD bias supply equals the voltage differential. With a wide operating range from 4.5 V to 18 V, the UCC2752x device can be used to drive a variety of power switches, such as Si MOSFETs (for example, VGS = 4.5 V, 10 V, 12 V), IGBTs (VGE = 15 V, 18 V).

9.2.2.4 Propagation Delay

The acceptable propagation delay from the gate driver is dependent on the switching frequency at which it is used and the acceptable level of pulse distortion to the system. The UCC2752x device features fast 13-ns (typical) propagation delays which ensures very little pulse distortion and allows operation at very high-frequencies. See the Switching Characteristics for the propagation and switching characteristics of the UCC2752x device.

9.2.2.5 Drive Current and Power Dissipation

The UCC27523/4/5/6 family of drivers are capable of delivering 5-A of current to a MOSFET gate for a period of several-hundred nanoseconds at V_DD = 12 V. High peak current is required to turn the device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground which repeats at the operating frequency of the power device. The power dissipated in the gate-driver device package depends on the following factors:

• Gate charge required of the power MOSFET (usually a function of the drive voltage V_GS, which is very close to input bias supply voltage V_DD due to low V_OH drop-out)
• Switching frequency
• Use of external gate resistors

Because UCC2752x features very low quiescent currents and internal logic to eliminate any shoot-through in the output driver stage, their effect on the power dissipation within the gate driver can be safely assumed to be negligible.

When a driver device is tested with a discrete, capacitive load calculating the power that is required from the bias supply is fairly simple. The energy that must be transferred from the bias supply to charge the capacitor is given by Equation 1.

Equation 1.

where

• C_LOAD is load capacitor
• V_DD is bias voltage feeding the driver.

There is an equal amount of energy dissipated when the capacitor is charged. This leads to a total power loss given by Equation 2.

Equation 2.

where

• f_SW is the switching frequency

With V_DD = 12 V, C_LOAD = 10 nF and ƒ_SW = 300 kHz the power loss is calculated as (see Equation 3):

Equation 3.

The switching load presented by a power MOSFET is converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Q_g, the power that must be dissipated when charging a capacitor is determined which by using the equivalence Q_g = C_LOADV_DD to provide Equation 4 for power:

Equation 4.

Assuming that UCC2752x is driving power MOSFET with 60 nC of gate charge (Q_g = 60 nC at V_DD = 12 V) on each output, the gate charge related power loss is calculated as (see Equation 5):

Equation 5.

This power PG is dissipated in the resistive elements of the circuit when the MOSFET turns on or turns off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is employed between the driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the use of external gate drive resistors, the power dissipation is shared between the internal resistance of driver and external gate resistor in accordance to the ratio of the resistances (more power dissipated in the higher resistance component). Based on this simplified analysis, the driver power dissipation during switching is calculated as follows (see Equation 6):

Equation 6.

where

• R_OFF = R_OL
• R_ON (effective resistance of pullup structure) = 1.5 x R_OL

In addition to the above gate-charge related power dissipation, additional dissipation in the driver is related to the power associated with the quiescent bias current consumed by the device to bias all internal circuits such as input stage (with pullup and pulldown resistors), enable, and UVLO sections. As shown in Figure 6, the quiescent current is less than 0.6 mA even in the highest case. The quiescent power dissipation is calculated easily with Equation 7.

Equation 7.

Assuming , I_DD = 6 mA, the power loss is:

Equation 8.

Clearly, this power loss is insignificant compared to gate charge related power dissipation calculated earlier.

With a 12-V supply, the bias current is estimated as follows, with an additional 0.6-mA overhead for the quiescent consumption:

Equation 9.