SLUSD37E October 2017 – November 2019 UCC28056
Voltage offset on the ZCD/CS pin is likely to result from high-amplitude switching edge spikes on the waveform applied to this pin. These switching edge spikes are clamped by any non-linear controller, such as the internal ESD structures, and upset the DC operating point of the divider. This can be observed as a voltage offset on the ZCD/CS pin signal, particularly at times when rate of change of current is highest (high load around the Line voltage peaks). When designing the ZCD/CS pin divider, prevent it from picking up switching edge spikes. Use of a low inductance type current sense resistor is also important for the same reason. If necessary an RC filter, with a time constant of approximately 30 ns, may be added between the voltage divider and the ZCD/CS pin to attenuate switching edge spikes. Ensure the capacitance (CZC3) of this filter is small relative to the value of CZC2. Limit the error introduced by the R-C filter to less than 1%, by ensuring that the series resistance is below the value calculated in Equation 67.
For this example design, the following values were selected for the RC filter to attenuate switching edge spikes.