SLUSD37E October   2017  – November 2019 UCC28056


  1. Features
  2. Applications
  3. Description
    1.     No Load Power
      1.      Device Images
        1.       Simplified Application
  4. Revision History
  5. Device Comparison Tables
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CrM/DCM Control Principle
      2. 8.3.2 Line Voltage Feed-Forward
        1. Peak Line Voltage Detection
      3. 8.3.3 Valley Switching and CrM/DCM Hysteresis
        1. Valley Delay Adjustment
      4. 8.3.4 Transconductance Amplifier with Transient Speed-up Function
      5. 8.3.5 Faults and Protections
        1. Supply Undervoltage Lockout
        2. Two Level Over-Current Protection
          1. Cycle-by-Cycle Current Limit Ocp1
          2. Ocp2 Gross Over-Current or CCM Protection
        3. Output Over-Voltage Protection
          1. First Level Output Over-Voltage Protection (Ovp1)
          2. Second Level Over-Voltage Protection (Ovp2)
        4. Thermal Shutdown Protection
        5. Line Under-Voltage or Brown-In
      6. 8.3.6 High-Current Driver
    4. 8.4 Controller Functional Modes
      1. 8.4.1 Burst Mode Operation
      2. 8.4.2 Soft Start
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Custom Design With WEBENCH® Tools
        2. Power Stage Design
          1. Boost Inductor Design
          2. Boost Switch Selection
          3. Boost Diode Selection
          4. Output Capacitor Selection
        3. ZCD/CS Pin
          1. Voltage Spikes on the ZCD/CS pin Waveform
        4. VOSNS Pin
        5. Voltage Loop Compensation
          1. Plant Model
          2. Compensator Design
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 VOSNS Pin
      2. 11.1.2 ZCD/CS Pin
      3. 11.1.3 VCC Pin
      4. 11.1.4 GND Pin
      5. 11.1.5 DRV Pin
      6. 11.1.6 COMP Pin
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


The VOSNS pin voltage is applied to the inverting input of an internal trasnconductance error amplifier. A fixed reference voltage (VOSReg) being applied to the non-inverting input. The error amplifier has high gain hence in steady-state, assuming VCOMP < 5-V, average voltage on the VOSNS pin must be approximately equal to the reference voltage (VOSReg). Output voltage regulation set point (VOutReg) is therefore determined by the external resistor divider network connecting the output voltage to the VOSNS pin according to the following expression.

Equation 70. UCC28056 eq-70.gif

The resistive divider that feeds the VOSNS pin makes a significant contribution to the unloaded input power. Higher resistor values reduce power consumption of the divider.

Equation 71. UCC28056 eq-71.gif

Regulation accuracy degrades with increased resistor values due to the effect of VOSNS pin bias current (IOSBias).

Equation 72. UCC28056 eq-72.gif

To ensure that VOSNS pin bias current degrades output voltage regulation by less than 1%, the upper voltage divider resistor value must be constrained as show in Equation 73.

Equation 73. UCC28056 eq-73.gif

Equation 73 confirms that reduction of the VOSNS divider dissipation to below 4 mW does not negatively affecting the regulation accuracy.

The PFC stage, of this design example, is to be followed by an LLC stage, that is controlled by UCC256301 device. The UCC28056 controller and the UCC256301 device operate together to form a complete off-Line power supply system with excellent light-load efficiency and standby power. To limit no-load input power a single resistor divider feeds both the VOSNS pin (UCC28056) and the BLK pin (UCC256301). A resistor divider with two taps is required because the UCC28056 requires a different divide ratio (KOS) to that required for the UCC256301 device (KBLK). The upper divider resistor (ROS1) is divided into two parts (ROS11, ROS12) to achieve the additional tap.

Equation 74. UCC28056 eq-74.gif
Equation 75. UCC28056 eq-75.gif

For this design example select an upper divider resistor made up of three series-connected, 3.24-MΩ, 1206 SMT resistors. This compact and cost-effective design produces a suitable high-voltage resistor. If a single resistor is preferred, use a high voltage type, rated for the maximum voltage that can appear across the output capacitor during a Line surge test.

Equation 76. UCC28056 eq-76.gif

Solving Equation 74 and Equation 75 simultaneously results in:

Equation 77. UCC28056 eq-77.gif
Equation 78. UCC28056 eq-78.gif

These two divider resistor values can be implemented using easily obtainable values as follows:

Equation 79. UCC28056 eq-79.gif
Equation 80. UCC28056 eq-80.gif

Actual regulation set point is therefore:

Equation 81. UCC28056 eq-81.gif

Power dissipated in the VOSNS resistor divider is:

Equation 82. UCC28056 eq-82.gif