SLUS161F April   1999  – May 2020 UCC2813-0 , UCC2813-1 , UCC2813-2 , UCC2813-3 , UCC2813-4 , UCC2813-5 , UCC3813-0 , UCC3813-1 , UCC3813-2 , UCC3813-3 , UCC3813-4 , UCC3813-5

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Block Diagram
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Descriptions
        1. 8.3.1.1 COMP
        2. 8.3.1.2 CS
        3. 8.3.1.3 FB
        4. 8.3.1.4 GND
        5. 8.3.1.5 OUT
        6. 8.3.1.6 RC
        7. 8.3.1.7 REF
        8. 8.3.1.8 VCC
      2. 8.3.2  Undervoltage Lockout (UVLO)
      3. 8.3.3  Self-Biasing, Active Low Output
      4. 8.3.4  Reference Voltage
      5. 8.3.5  Oscillator
      6. 8.3.6  Synchronization
      7. 8.3.7  PWM Generator
      8. 8.3.8  Minimum Off-Time Adjustment (Dead-Time Control)
      9. 8.3.9  Leading Edge Blanking
      10. 8.3.10 Minimum Pulse Width
      11. 8.3.11 Current Limiting
      12. 8.3.12 Overcurrent Protection and Full-Cycle Restart
      13. 8.3.13 Soft Start
      14. 8.3.14 Slope Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
      3. 8.4.3 Soft-Start Mode
      4. 8.4.4 Fault Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Bulk Capacitor Calculation
        2. 9.2.2.2  Transformer Design
        3. 9.2.2.3  MOSFET and Output Diode Selection
        4. 9.2.2.4  Output Capacitor Calculation
        5. 9.2.2.5  Current Sensing Network
        6. 9.2.2.6  Gate Drive Resistor
        7. 9.2.2.7  REF Bypass Capacitor
        8. 9.2.2.8  RT and CT
        9. 9.2.2.9  Start-Up Circuit
        10. 9.2.2.10 Voltage Feedback Compensation Procedure
          1. 9.2.2.10.1 Power Stage Gain, Zeroes, and Poles
          2. 9.2.2.10.2 Compensating the Loop
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
  • PW|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power Stage Gain, Zeroes, and Poles

The first step in compensating a fixed-frequency flyback is to verify if the converter operates in continuous conduction mode (CCM) or discontinuous conduction mode (DCM). If the primary inductance (LP) is greater than the inductance for DCM-CCM boundary mode operation, called the critical inductance (LPcrit), then the converter operates in CCM. LPcrit is calculated with Equation 17.

Equation 17. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_19_SLUS270.gif

For loads greater than 10% of PMAX over the entire input voltage range, the selected primary inductance has value larger than the critical inductance. Therefore, the converter operates in CCM and the compensation loop requires design based on CCM flyback equations.

The current-to-voltage conversion is done externally with the ground-referenced current-sense resistor (RCS) and the internal resistor divider sets up the internal current-sense gain, ACS = 1.65. The IC technology allows tight control of the resistor-divider ratio, regardless of the actual resistor value variations.

The DC open-loop gain (GO) of the fixed-frequency voltage control loop of a peak-current-mode control CCM flyback converter shown in Figure 33 is approximated by first using the output load (ROUT), the primary to secondary turns ratio (NPS), and the maximum duty cycle (D) as shown in Equation 18.

Equation 18. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_20_SLUS270.gif

where

Equation 19. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_21_SLUS270.gif
Equation 20. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_22_SLUS270.gif
Equation 21. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_23_SLUS270.gif

For this design, a converter with an output voltage (VOUT) of 12 V, and 48 W relates to an output load (ROUT) equal to 3 Ω at full load.

At minimum input bulk voltage of 75 V DC, the duty cycle reaches its maximum value of 0.615. The current sense resistance (RCS) is 0.75 Ω and a primary to secondary turns-ratio (NPS) is 10. The open-loop gain calculates to 14.95 dB.

A CCM flyback transfer function has two zeroes that are of interest. The ESR and the output capacitance contribute a left-half plane zero to the power stage, and the frequency of this zero (fESRz) is calculated with Equation 22.

Equation 22. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_24_SLUS270E.gif

The fESRz zero for a capacitance bank of three 680-µF capacitors (for a total output capacitance of 2040 µF) and a total ESR of 13 mΩ is located at 6 kHz.

CCM flyback converters have a zero in the right-half plane (RHP) of their transfer function. RHP zero has the same 20 dB/decade rising gain magnitude with increasing frequency just like a left-half plane zero, but it adds phase lag instead of lead. This phase lag tends to limit the overall loop bandwidth. The frequency location (fRHPz) in Equation 23 is a function of the output load, the duty cycle, the primary inductance (LP), and the primary to secondary side turns ratio (NPS).

Equation 23. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_27_SLUS270.gif

RHP zero frequency increases with higher input voltage and lighter load. Generally, the design requires consideration of the worst case of the lowest RHP zero frequency and the converter must be compensated at the minimum input and maximum load condition. With a primary inductance of 1.5 mH, at 75-V DC input, the RHP zero frequency (fRHPz) is equal to 7.65 kHz at maximum duty cycle (full load).

The power stage has one dominant pole (ωP1) which is in the region of interest, located at a lower frequency (fP1) which is related to the duty cycle (D), the output load, and the output capacitance. There is also a double pole (fP2) located at half the switching frequency of the converter. These poles are frequencies calculated with Equation 24 and Equation 25.

Equation 24. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_28_SLUS270.gif
Equation 25. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_31_SLUS270.gif

Subharmonic oscillation is the large signal instability that can occur in CCM flyback converters when duty cycles extend beyond 50%. The subharmonic oscillation increases the output voltage ripple and sometimes it even limits the power handling capability of the converter. Slope compensation to the CS signal is a technique used to eliminate the instability.

Ideally, the target of slope compensation is to achieve quality coefficient (QP = 1) at half of the switching frequency. The QP is calculated by Equation 26.

Equation 26. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_32_SLUS270.gif

where

  • D is the primary side switch duty cycle
  • MC is the slope compensation factor, which is defined by Equation 27
Equation 27. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_32a_SLUS270.gif

where

  • Se is the compensation ramp slope
  • Sn represents the rising current slope of the transformer primary inductance

The optimal goal of the slope compensation is to achieve QP equal to 1, which means MC must be 2.128 when D reaches it maximum value of 0.615.

The inductance current slope at the CS pin is calculated by Equation 28.

Equation 28. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 EqSn.gif

The compensation slope is calculated by Equation 29.

Equation 29. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_32c_SLUS270.gif

The compensation slope is added into the system through RRAMP and RCSF. A series capacitor (CRAMP) is selected to approximate a high-frequency short circuit. Choose CRAMP as 10 nF as the starting point, and make adjustments if required. RRAMP and RCSF form a voltage divider to scale the RC pin ramp voltage and inject the slope compensation into CS pin. Choose RRAMP much larger than the RT resistor so that it does not affect the frequency setting very much. In this design, RRAMP is selected as 24.9 kΩ. The RC pin ramp slope is calculated with Equation 30.

Equation 30. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_32d_SLUS270.gif

To achieve 46.3 mV/µs compensation slope, RCSF resistor is calculated with Equation 31.

Equation 31. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Eqn_33_SLUS161.gif

The power stage open-loop gain and phase can be plotted as a function of frequency. The total open-loop transfer function, as a function of frequency, can be characterized by Equation 32.

Equation 32. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Eqn_34_SLUS161.gif

where

The open-loop gain and phase Bode plots are graphed accordingly (see Figure 34 and Figure 35).

UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Figure_35A_SLUS270E.gifFigure 34. Converter Open-Loop Bode Plot: Gain
UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Figure_35B_SLUS270E.gifFigure 35. Converter Open-Loop Bode Plot: Phase