SLUSBW3D March   2014  – December 2017 UCC28630 , UCC28631 , UCC28632 , UCC28633 , UCC28634

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Typical Application Measured Regulation
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     PIN Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information (UCC28630, UCC28631)
    5. 7.5 Thermal Information (UCC28632, UCC28633, (UCC28630, UCC28634)
    6. 7.6 Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High-Voltage Current Source Start-Up Operation
      2. 8.3.2  AC Input UVLO / Brownout Protection
      3. 8.3.3  Active X-Capacitor Discharge (UCC28630 and UCC28633 only)
        1. 8.3.3.1 Improved Performance with UCC28630 and UCC28633
      4. 8.3.4  Magnetic Input and Output Voltage Sensing
      5. 8.3.5  Fixed-Point Magnetic Sense Sampling Error Sources
      6. 8.3.6  Magnetic Sense Resistor Network Calculations
        1. 8.3.6.1 Step 1
        2. 8.3.6.2 Step 2
        3. 8.3.6.3 Step 3
        4. 8.3.6.4 Step 4
      7. 8.3.7  Magnetic Sensing: Power Stage Design Constraints
      8. 8.3.8  Magnetic Sense Voltage Control Loop
      9. 8.3.9  Peak Current Mode Control
      10. 8.3.10 IPEAK Adjust vs. Line
      11. 8.3.11 Primary-Side Constant-Current Limit (CC Mode)
      12. 8.3.12 Primary-Side Overload Timer (UCC28630 only)
      13. 8.3.13 Overload Timer Adjustment (UCC28630 only)
      14. 8.3.14 CC-Mode IOUT(lim) Adjustment
      15. 8.3.15 Fault Protections
      16. 8.3.16 Pin-Fault Detection and Protection
      17. 8.3.17 Over-Temperature Protection
      18. 8.3.18 External Fault Input
      19. 8.3.19 External SD Pin Wake Input (except UCC28633)
      20. 8.3.20 External Wake Input at VSENSE Pin (UCC28633 Only)
      21. 8.3.21 Mode Control and Switching Frequency Modulation
      22. 8.3.22 Frequency Dither For EMI (except UCC28632)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Internal Key Parameters
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Notebook Adapter, 19.5 V, 65 W
      2. 9.2.2 UCC28630 Application Schematic
      3. 9.2.3 Design Requirements
      4. 9.2.4 Detailed Design Procedure
        1. 9.2.4.1  Custom Design With WEBENCH® Tools
        2. 9.2.4.2  Input Bulk Capacitance and Minimum Bulk Voltage
        3. 9.2.4.3  Transformer Turn Ratio
        4. 9.2.4.4  Transformer Magnetizing Inductance
        5. 9.2.4.5  Current Sense Resistor RCS
        6. 9.2.4.6  Transformer Constraint Verification
        7. 9.2.4.7  Transformer Selection and Design
        8. 9.2.4.8  Slope Compensation Verification
        9. 9.2.4.9  Power MOSFET and Output Rectifier Selection
        10. 9.2.4.10 Output Capacitor Selection
        11. 9.2.4.11 Calculation of CC Mode Limit Point
        12. 9.2.4.12 VDD Capacitor Selection
        13. 9.2.4.13 Magnetic Sense Resistor Network Selection
        14. 9.2.4.14 Output LED Pre-Load Resistor Calculation
      5. 9.2.5 External Wake Pulse Calculation at VSENSE Pin (UCC28633 Only)
      6. 9.2.6 Energy Star Average Efficiency and Standby Power
      7. 9.2.7 Application Performance Plots
    3. 9.3 Dos and Don'ts
      1. 9.3.1 Test and Debug Recommendations
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 HV Pin
      2. 11.1.2 VDD Pin
      3. 11.1.3 VSENSE Pin
      4. 11.1.4 CS Pin
      5. 11.1.5 SD Pin
      6. 11.1.6 DRV Pin
      7. 11.1.7 GND Pin
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
        1. 12.2.1.1 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3.1 Improved Performance with UCC28630 and UCC28633

In order to reduce standby power and eliminate the standing loss associated with the conventional discharge resistors, the UCC28630 and the UCC28633 devices incorporate active X-capacitor discharge circuitry. This circuit periodically monitors the voltage across the X-capacitor to detect any possible DC-condition (which would indicate that AC mains disconnection has occurred), and then discharges the voltage across the X-capacitor using the internal HV current source. The X-capacitor discharge function discharges the X-capacitor to the SELV 60-V level in 1 s (as long as the design considerations discussed in this section are followed).

The device internally monitors the current into the HV pin to determine if the voltage across the X-capacitor in the EMI filter has a sufficient AC ripple component. If insufficient AC content is detected, then a DC condition is internally flagged. This causes the controller to enter low-power mode for the reset period (tRESET(short)), followed by bias voltage discharge to the reset level (VDD(reset)) , and then the start-up HV current source turns on again to effectively discharge the X-capacitor by transferring charge to the VDD reservoir capacitor.

Because the device monitors the HV pin to detect a DC condition on the X-capacitor, the system cannot operate with DC input to the HV pin. Instead, the HV pin must be connected to an AC source only. The device interprets any DC input on the HV pin as DC across the X-capacitor, indicating an AC-disconnect event. This causes a repeating cycle of start-up and shutdown. The device requires an external 200-kΩ of resistance on the HV pin, to limit the current to a level below the saturation point of the internal HV current source. This limit produces a HV input current that is approximately proportional to AC line, so that the AC content can be sensed.

The size of the X-capacitor that can be discharged depends on the VDD energy storage capacitor. Assuming the worst case, a maximum X-capacitor disconnect voltage could be at the peak of 264 VRMS, and assuming that it should be discharged down to 60-V SELV level, the minimum allowed VDD capacitor can be sized based on the worst case VDD(reset) and VDD(start) levels as described in Equation 3.

Equation 3. UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 qu4_lusbw3.gif

For example, for a 330-nF X-capacitor value, the required VDD capacitor is 15.9 µF, so a 22-µF capacitor suffices.

Equation 4. UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 qu5_lusbw3.gif

In order to reduce the power consumption from the high voltage AC line, the device pulses current into the HV pin at a low frequency with very low duty-cycle. The HV current source on-time (tON(HV)) , repeats at intervals of tSMP(HV). Moreover, the pulsing occurs in bursts, with a time delay between bursts. The sampling occurs in bursts of 21, at intervals of tSMP(HV), with a wait time of tWAIT(HV) between bursts. This reduces the effective average duty-cycle to a very low value (approximately 0.2%), and minimizes the overhead of X-capacitor sampling current and device bias consumption overhead to approximately 2 mW of extra standby consumption at high-line 230 VAC.

The device enables the X-capacitor monitor in latched fault mode, and in light-load regions where the power level is below PLL(%), as a percentage of the nominal rated level. Above the PLL(%) level, the X-capacitor monitor is disabled. At this load level the bulk capacitor discharges at a rate that is sufficient to also discharge the X-capacitor, which appears in parallel with the bulk capacitor once the bulk voltage drops far enough to forward bias the bridge rectifier diodes. In this case ensure that the bulk capacitance value is not too large for the power level desired, which in-turn ensures that the bulk capacitor discharge rate is fast enough to discharge the X-capacitor to meet the 1-s discharge target. This can be calculated in Equation 5.

Equation 5. UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 qu6_lusbw3.gif

Assuming a worst case AC disconnect at the peak at 264 VRMS (373 VPK), and a requirement to discharge to SELV level of 60 V in tXCAP(dis) of 1 s, for a PNOM of 65 W at 87% efficiency, this is calculated in Equation 6.

Equation 6. UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 qu7_lusbw3.gif

Once the bulk capacitance value is chosen, also ensure that when the bulk capacitor has been discharged down to the line UV ACOFF threshold, that it continues to discharge to an acceptable level during the line UV persistence delay time (tUV(delay)) as shown in Equation 7.

Equation 7. UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 Eq7.gif

Again, taking the example above:

Equation 8. UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 qu9_lusbw3.gif

Once the first constraint is satisfied, the second one is also automatically met.

UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 fig22_lusbw3.gifFigure 19. X-Capacitor Discharge Activation, at 230 VAC, No Load
(red = X-capacitor, blue = bulk-capacitor, both 100 V/div)
UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 fig21_lusbw3.gifFigure 20. X-Capacitor Decay Rate Without Active Discharge
(time constant dominated by 20-MΩ probe impedance)
(red = X-capacitor, blue = bulk-capacitor, both 100 V/div)