SLUSBL5A February   2015  – June 2019 UCC28730


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Zero-Power Input Consumption at No-Load
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
        1. VDD (Device Bias Voltage Supply)
        2. GND (Ground)
        3. HV (High Voltage Startup)
        4. DRV (Gate Drive)
        5. CBC (Cable Compensation)
        6. VS (Voltage Sense)
        7. CS (Current Sense)
      2. 7.3.2 Primary-Side Regulation (PSR)
      3. 7.3.3 Primary-Side Constant Voltage Regulation
      4. 7.3.4 Primary-Side Constant Current Regulation
      5. 7.3.5 Wake-Up Detection and Function
      6. 7.3.6 Valley-Switching and Valley-Skipping
      7. 7.3.7 Startup Operation
      8. 7.3.8 Fault Protection
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Stand-By Power Estimate
        2. Input Bulk Capacitance and Minimum Bulk Voltage
        3. Transformer Turns Ratio, Inductance, Primary-Peak Current
        4. Transformer Parameter Verification
        5. Output Capacitance
        6. VDD Capacitance, CVDD
        7. VS Resistor Divider, Line Compensation, and Cable Compensation
        8. VS Wake-Up Detection
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
      2. 11.1.2 Device Nomenclature
        1.  Capacitance Terms in Farads
        2.  Duty-Cycle Terms
        3.  Frequency Terms in Hertz
        4.  Current Terms in Amperes
        5.  Current and Voltage Scaling Terms
        6.  Transformer Terms
        7.  Power Terms in Watts
        8.  Resistance Terms in Ω
        9.  Timing Terms in Seconds
        10. DC Voltage Terms in Volts
        11. AC Voltage Terms in Volts
        12. Efficiency Terms
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Primary-Side Regulation (PSR)

Figure 13 illustrates a simplified isolated-flyback convertor with the main voltage regulation blocks of the device shown. The power train operation is the same as any DCM flyback circuit but accurate output voltage and current sensing is the key to primary-side control. The output voltage is sensed as a reflected voltage during the transformer demagnetization time using a divider network at the VS input. The primary winding current is sensed at the CS input using a current-sense resistor, RCS.

UCC28730 vreg_blk_lusbl5.gifFigure 13. Simplified Flyback Convertor (with the main voltage regulation blocks)

In primary-side control, the output voltage is indirectly sensed on the auxiliary winding at the end of the transfer of stored transformer energy to the secondary. As shown in Figure 14 it is clear there is a down slope representing a decreasing total rectifier VF and resistance voltage drop as the secondary current decreases to zero. To achieve an accurate representation of the secondary output voltage on the auxiliary winding, the discriminator reliably blocks the leakage inductance reset and ringing, continuously samples the auxiliary voltage during the down slope after the ringing is diminished, and captures the error signal at the time the secondary winding reaches zero current. The internal reference on VS is 4.04 V. Temperature compensation on the VS reference voltage of -1 mV/°C offsets the change in the forward voltage of the output rectifier with temperature. The resistor divider is selected as outlined in the VS pin description.

UCC28730 vaux_lusbl5.gifFigure 14. Auxiliary Winding Voltage

The UCC28730 VS-signal sampler includes signal discrimination methods to ensure an accurate sample of the output voltage from the auxiliary winding. There are, however, some details of the auxiliary winding signal which require attention to ensure reliable operation, specifically the reset time of the leakage inductance and the duration of any subsequent leakage inductance ring. Refer to Figure 15 below for a detailed illustration of waveform criteria to ensure a reliable sample on the VS pin.

UCC28730 vaux_dtl_lusbl5.gifFigure 15. Auxiliary Waveform Details

The first detail to examine is the duration of the leakage inductance reset pedestal, tLK_RESET in Figure 15. Since this can mimic the waveform of the secondary current decay, followed by a sharp downslope, it is important to keep the leakage reset time to less than 750 ns for IPRI minimum, and to less than 2.25 µs for IPRI maximum.

The second detail is the amplitude of ringing on the VAUX waveform following tLK_RESET. The peak-to-peak voltage at the VS pin should be less than 125 mV for at least 200 ns before the end of the demagnetization time, tDM. If there is a concern with excessive ringing, it usually occurs during light-load or no-load conditions, when tDM is at the minimum. To avoid distorting the signal waveform at VS with oscilloscope probe capacitance, it is recommended to probe the auxiliary winding to view the VS waveform characteristics. The tolerable ripple on VS is scaled up to the auxiliary-winding voltage by RS1 and RS2, and is equal to 125 mV x (RS1 + RS2) / RS2.