SLUSBL5A February 2015 – June 2019 UCC28730
Figure 13 illustrates a simplified isolated-flyback convertor with the main voltage regulation blocks of the device shown. The power train operation is the same as any DCM flyback circuit but accurate output voltage and current sensing is the key to primary-side control. The output voltage is sensed as a reflected voltage during the transformer demagnetization time using a divider network at the VS input. The primary winding current is sensed at the CS input using a current-sense resistor, RCS.
In primary-side control, the output voltage is indirectly sensed on the auxiliary winding at the end of the transfer of stored transformer energy to the secondary. As shown in Figure 14 it is clear there is a down slope representing a decreasing total rectifier VF and resistance voltage drop as the secondary current decreases to zero. To achieve an accurate representation of the secondary output voltage on the auxiliary winding, the discriminator reliably blocks the leakage inductance reset and ringing, continuously samples the auxiliary voltage during the down slope after the ringing is diminished, and captures the error signal at the time the secondary winding reaches zero current. The internal reference on VS is 4.04 V. Temperature compensation on the VS reference voltage of -1 mV/°C offsets the change in the forward voltage of the output rectifier with temperature. The resistor divider is selected as outlined in the VS pin description.
The UCC28730 VS-signal sampler includes signal discrimination methods to ensure an accurate sample of the output voltage from the auxiliary winding. There are, however, some details of the auxiliary winding signal which require attention to ensure reliable operation, specifically the reset time of the leakage inductance and the duration of any subsequent leakage inductance ring. Refer to Figure 15 below for a detailed illustration of waveform criteria to ensure a reliable sample on the VS pin.
The first detail to examine is the duration of the leakage inductance reset pedestal, tLK_RESET in Figure 15. Since this can mimic the waveform of the secondary current decay, followed by a sharp downslope, it is important to keep the leakage reset time to less than 750 ns for IPRI minimum, and to less than 2.25 µs for IPRI maximum.
The second detail is the amplitude of ringing on the VAUX waveform following tLK_RESET. The peak-to-peak voltage at the VS pin should be less than 125 mV for at least 200 ns before the end of the demagnetization time, tDM. If there is a concern with excessive ringing, it usually occurs during light-load or no-load conditions, when tDM is at the minimum. To avoid distorting the signal waveform at VS with oscilloscope probe capacitance, it is recommended to probe the auxiliary winding to view the VS waveform characteristics. The tolerable ripple on VS is scaled up to the auxiliary-winding voltage by RS1 and RS2, and is equal to 125 mV x (RS1 + RS2) / RS2.