SLUSDT2C August   2019  – December 2020 UCC28740-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
      2. 7.3.2 Valley-Switching and Valley-Skipping
      3. 7.3.3 Startup Operation
      4. 7.3.4 Fault Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation
      2. 7.4.2 Primary-Side Constant-Current (CC) Regulation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 High Voltage Applications
    3. 8.3 Typical Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
        1. 8.3.2.1  Custom Design With WEBENCH® Tools
        2. 8.3.2.2  Standby Power Estimate and No-Load Switching Frequency
        3. 8.3.2.3  Input Bulk Capacitance and Minimum Bulk Voltage
        4. 8.3.2.4  35
        5. 8.3.2.5  Transformer Turns-Ratio, Inductance, Primary Peak Current
        6. 8.3.2.6  Transformer Parameter Verification
        7. 8.3.2.7  VS Resistor Divider, Line Compensation
        8. 8.3.2.8  Output Capacitance
        9. 8.3.2.9  VDD Capacitance, CVDD
        10. 8.3.2.10 Feedback Network Biasing
      3. 8.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 VDD Pin
      2. 10.1.2 VS Pin
      3. 10.1.3 FB Pin
      4. 10.1.4 GND Pin
      5. 10.1.5 CS Pin
      6. 10.1.6 DRV Pin
      7. 10.1.7 HV Pin
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1  Capacitance Terms in Farads
        2. 11.1.2.2  Duty Cycle Terms
        3. 11.1.2.3  Frequency Terms in Hertz
        4. 11.1.2.4  Current Terms in Amperes
        5. 11.1.2.5  Current and Voltage Scaling Terms
        6. 11.1.2.6  Transformer Terms
        7. 11.1.2.7  Power Terms in Watts
        8. 11.1.2.8  Resistance Terms in Ohms
        9. 11.1.2.9  Timing Terms in Seconds
        10. 11.1.2.10 Voltage Terms in Volts
        11. 11.1.2.11 AC Voltage Terms in VRMS
        12. 11.1.2.12 Efficiency Terms
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks

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Orderable Information

8.3.2.9 VDD Capacitance, CVDD

The capacitance on VDD must supply the primary-side operating current used during startup and between low-frequency switching pulses. The largest result of three independent calculations denoted in Equation 28, Equation 29, and Equation 30 determines the value of CVDD.

At startup, when VVDD(on) is reached, CVDD alone supplies the device operating current and MOSFET gate current until the output of the converter reaches the target minimum-operating voltage in CC regulation, VOCC. Now the auxiliary winding sustains VDD for the UCC28740-Q1 above UVLO. The total output current available to the load and to charge the output capacitors is the CC-regulation target, IOCC. Equation 28 assumes that all of the output current of the converter is available to charge the output capacitance until VOCC is achieved. For typical applications, Equation 28 includes an estimated qGfSW(max) of average gate-drive current and a 1-V margin added to VVDD.

Equation 28. GUID-E9125FC8-58DA-4BFD-A2E2-E3B10D428B0C-low.gif

During a worst-case un-load transient event from full-load to no-load, COUT overcharges above the normal regulation level for a duration of tOV, until the output shunt-regulator loading is able to drain VOUT back to regulation. During tOV, the voltage feedback loop and optocoupler are saturated, driving maximum IFB and temporarily switching at fSW(min). The auxiliary bias current expended during this situation exceeds that normally required during the steady-state no-load condition. Equation 29 calculates the value of CVDD (with a safety factor of 2) required to ride through the tOV duration until steady-state no-load operation is achieved.

Equation 29. GUID-F96EE5E4-48D7-4BE5-8BAD-BBB20CCD39AF-low.gif

Finally, in the steady-state no-load operating condition, total no-load auxiliary-bias current, IAUXNL is provided by the converter switching at a no-load frequency, fSWNL, which is generally higher than fSW(min). CVDD is calculated to maintain a target VDD ripple voltage lower than ΔVVDD, using Equation 30.

Equation 30. GUID-0AC67B45-74D6-4612-99BF-63585494406A-low.gif