SLUSBF3D July   2013  – March 2018 UCC28740

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application Diagram
      2.      Typical V-I Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
      2. 7.3.2 Valley-Switching and Valley-Skipping
      3. 7.3.3 Startup Operation
      4. 7.3.4 Fault Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation
      2. 7.4.2 Primary-Side Constant-Current (CC) Regulation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Standby Power Estimate and No-Load Switching Frequency
        3. 8.2.2.3 Input Bulk Capacitance and Minimum Bulk Voltage
        4. 8.2.2.4 Transformer Turns-Ratio, Inductance, Primary Peak Current
        5. 8.2.2.5 Transformer Parameter Verification
        6. 8.2.2.6 VS Resistor Divider, Line Compensation
        7. 8.2.2.7 Output Capacitance
        8. 8.2.2.8 VDD Capacitance, CVDD
        9. 8.2.2.9 Feedback Network Biasing
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 VDD Pin
      2. 10.1.2 VS Pin
      3. 10.1.3 FB Pin
      4. 10.1.4 GND Pin
      5. 10.1.5 CS Pin
      6. 10.1.6 DRV Pin
      7. 10.1.7 HV Pin
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1  Capacitance Terms in Farads
        2. 11.1.2.2  Duty Cycle Terms
        3. 11.1.2.3  Frequency Terms in Hertz
        4. 11.1.2.4  Current Terms in Amperes
        5. 11.1.2.5  Current and Voltage Scaling Terms
        6. 11.1.2.6  Transformer Terms
        7. 11.1.2.7  Power Terms in Watts
        8. 11.1.2.8  Resistance Terms in Ohms
        9. 11.1.2.9  Timing Terms in Seconds
        10. 11.1.2.10 Voltage Terms in Volts
        11. 11.1.2.11 AC Voltage Terms in VRMS
        12. 11.1.2.12 Efficiency Terms
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Transformer Turns-Ratio, Inductance, Primary Peak Current

The target maximum switching frequency at full-load, the minimum input-capacitor bulk voltage, and the estimated DCM resonant time determine the maximum primary-to-secondary turns-ratio of the transformer.

Initially determine the maximum-available total duty-cycle of the on-time and secondary conduction time based on the target switching frequency, fMAX, and DCM resonant time. For DCM resonant frequency, assume 500 kHz if an estimate from previous designs is not available. At the transition-mode operation limit of DCM, the interval required from the end of secondary current conduction to the first valley of the VDS voltage is ½ of the DCM resonant period (tR), or 1 µs assuming 500 kHz resonant frequency. The maximum allowable MOSFET on-time DMAX is determined using Equation 12.

Equation 12. UCC28740 q_Dmax_lusbf3.gif

When DMAX is known, the maximum primary-to-secondary turns-ratio is determined with Equation 13. DMAGCC is defined as the secondary-diode conduction duty-cycle during CC operation and is fixed internally by the UCC28740 at 0.425. The total voltage on the secondary winding must be determined, which is the sum of VOCV, VF, and VOCBC. For the 5-V USB-charger applications, a turns ratio range of 13 to 15 is typically used.

Equation 13. UCC28740 q_dp_Npsmax_lusb41.gif

A higher turns-ratio generally improves efficiency, but may limit operation at low input voltage. Transformer design iterations are generally necessary to evaluate system-level performance trade-offs. When the optimum turns-ratio NPS is determined from a detailed transformer design, use this ratio for the following parameters.

The UCC28740 constant-current regulation is achieved by maintaining DMAGCC at the maximum primary peak current setting. The product of DMAGCC and VCST(max) defines a CC-regulating voltage factor VCCR which is used with NPS to determine the current-sense resistor value necessary to achieve the regulated CC target, IOCC (see Equation 14).

Because a small portion of the energy stored in the transformer does not transfer to the output, a transformer-efficiency term is included in the RCS equation. This efficiency number includes the core and winding losses, the leakage-inductance ratio, and a bias-power to maximum-output-power ratio. An overall-transformer efficiency of 0.91 is a good estimate based on 3.5% leakage inductance, 5% core & winding loss, and 0.5% bias power, for example. Adjust these estimates as appropriate based on each specific application.

Equation 14. UCC28740 qu14_lusb86.gif

The primary transformer inductance is calculated using the standard energy storage equation for flyback transformers. Primary current, maximum switching frequency, output voltage and current targets, and transformer power losses are included in Equation 16.

First, determine the transformer primary peak current using Equation 15. Peak primary current is the maximum current-sense threshold divided by the current-sense resistance.

Equation 15. UCC28740 q_dp_Ippmax_lusb41.gif
Equation 16. UCC28740 q_dp_Lp_lusb41.gif

NAS is determined by the lowest target operating output voltage while in constant-current regulation and by the VDD UVLO turnoff threshold of the UCC28740. Additional energy is supplied to VDD from the transformer leakage-inductance which allows a lower turns ratio to be used in many designs.

Equation 17. UCC28740 q_Nas_lusbf3.gif